Dec. 15 ’97
I
2
C-bus Serial Interface
Real Time Clock (8pin SSOP)
RS5C372B
s
OUTLINE
The RS5C372B is a CMOS type real-time clock which is connected to the CPU via 2-wire and capable of serial
transmission of clock and calendar data to the CPU. The RS5C372B can generate various periodic interrupt
clock pulses lasting for long period (one month), and alarm interrupt can be made by days of the week, hours,
and minutes by two incorporated systems. Since an oscillation circuit is driven at a constant voltage, it
undergoes fluctuations of few voltage and consequently offers low current consumption (0.5µA at 3V). It also
provides an oscillator halt sensing function applicable for data validation at power-on and other occasions and
32kHz clock output (CMOS output) for an external micro computer. The product also incorporates a time
trimming circuit that adjusts the clock with higher precision by adjusting any errors in crystal oscillator
frequencies based on signals from the CPU. The crystal oscillator may be selected between 32.768kHz or
32.000kHz types. Integrated into an ultra compact and ultra thin 8 pin SSOP package, the RS5C372B is the
optimum choice for equipment requiring small sized and low power consuming products.
s
Features
q
Time keeping voltage 1.45V to 6.0V
q
Lowest supply current 0.5µA TYP (0.9µA MAX) at 3V(25°C)
(0.9µA MAX) at 3V(-40 to +85°C)
2
q
Connected to the CPU via only 2-wire (I C-bus interface, max.400KHz, address 7bits)
q
A clock counter (hours, minutes, and seconds) and a calendar counter (leap years, years, months, days,
and days of the week) in BCD codes
q
Interrupt to the CPU (period of one month to half second, with interrupt flag, interrupt halt function)
(/INTR)
q
Two systems of alarm functions (days of the week, hours, and minutes) (/INTR)
q
Oscillation halt sensing to judge internal data validity
q
Clock output of 32.768kHz(32.000kHz) ( output controllable via a register)
(32KOUT:CMOS push-pull output)
q
Second digit adjustment by ±30 seconds
q
Automatic leap year recognition up to the year 2099
q
12-hour or 24-hour time display selectable
q
Oscillation stabilizing capacity (CG, CD) incorporated
q
High precision clock error adjustment circuit
q
Oscillator of 32.768kHz or 32.000kHz may be used
q
CMOS logic
q
Package:8pin SSOP
2
*) I C-bus is a trademark of PHILIPS ELECTRONICS N.V.
s
Block Diagram
COMPARATOR_A
32KOUT
32kHz OUTPUT
CONTROL
COMPARATOR_B
OSCIN
OSC
OSCOUT
ALARM_A REGISTER
(WEEK,MIN,HOUR)
ALARM_B REGISTER
(WEEK,MIN,HOUR)
VDD
DIVIDER
CORREC
-TION
DIV
TIME COUNTER
(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)
VSS
OSC
DETECT
ADDRESS
DECODER
ADDRESS
REGISTER
SCL
I/O
CONTROL
/INTR
INTERRUPT CONTROL
SHIFT REGISTER
SDA
-1-
RS5C372B
s
Pin Configuration
RS5C372B (8PIN SSOP)
32KOUT
SCL
SDA
VSS
1
2
3
4
8
7
6
5
VDD
OSCIN
OSCOUT
/INTR
TOP VIEW
s
Pin Description
Symbol
SCL
SDA
Pin Name
Description
Shift clock input This pin is used to input shift clock pulses to synchronize data input/output to
and from the SDA pin with this clock. Up to 6V beyond VDD may be input.
Serial input
This pin inputs and outputs written or read data in synchronization with shift
output
clock pulses from the SCL pin. Up to 6V beyond VDD may be input. This
pin functions as an Nch open drain output.
Interrupt
output
32K Clock
Output
Oscillator
circuit
input/output
Positive power
supply input
Negative power
supply input
This pin outputs periodic interrupt pulses and alarm interrupt (ALARM_A,
ALARM_B) to the CPU. This pin is off when power is activated from 0V.
This pin functions as an Nch open drain output.
This pin outputs 32.768kHz pulses (when 32.768kHz crystal is used),
It outputs 32.768kHz when power source is activated from 0V. This pin
functions as an CMOS push-pull output.
These pins configure an oscillator circuit by connecting a 32.768kHz or
32.000kHz crystal oscillator between the OSCIN–OSCOUT pins.
(Any other oscillator circuit components are built into the RS5C372B.)
The VDD pin is connected to the positive power supply and Vss to the
ground.
/INTR
32KOUT
OSCIN
OSCOUT
VDD
VSS
-2-
RS5C372B
s
DC Characteristics
Unless otherwise specified: VSS=0V, VDD=3V, Topt=-40 to +85
°C
, Oscillation Frequency=32.768kHz or 32.000KHz(R1=30k
Ω
)
Symbol
VIH
VIL
IOH
IOL1
IOL2
IILK
IOZ
IDD1
Item
“H” input Voltage
“L” input voltage
“H” output current
“L” output current
Input leakage
current
Output off state
leakage current
Standby current
Pin Name
SCL,
SCL,
SDA
SDA
Conditions
MIN.
0.8
VDD
-0.3
TYP.
MAX.
6.0
0.2
VDD
-0.5
Unit
V
V
mA
mA
32KOUT
/INTR, 32KOUT
SDA
SCL
SDA, /INTR,
32KOUT
VDD
VOH=VDD-0.5V
VOL1=0.4V
VOL2=0.6V
VI=6V or VSS
VDD=6V
VO=6V or VSS
VDD=6V
VDD=3V, Topt=25°C
SCL,SDA=3V
Output=OPEN
*)
0.5
-1
1
6
-1
1
1
0.9
µA
µA
µA
IDD2
VDD
VDD=3V,
Topt=-40 to +85°C
SCL,SDA=3V
Output=OPEN
*)
0.8
*)
10
10
1.0
µA
IDD3
VDD
VDD=6V
SCL,SDA=6V
Output=OPEN
2.0
µA
CG
CD
Internal oscillation OSCIN
capacitance 1
Internal oscillation
capacitance 2
OSCOUT
pF
pF
*) The mode outputs no clock pulses and output is open (output off state).
For consumption current (output: no load) when 32kHz pulses are output from 32KOUT, see "Typical
Characteristics Measurement ".
-4-
RS5C372B
s
AC Characteristics
Unless otherwise specified: VSS=0V,Topt=-40 to +85°C
I/O Conditions: VIH=0.8×VDD,VIL=0.2×VDD,VOL=0.2×VDD,CL=50pF
Symbol
Item
VDD≥2.0V
VDD≥2.5V
Condi-
tions
MIN. TYP. MAX. MIN. TYP. MAX.
f
SCL
SCL clock frequency
0
100
0
400
t
LOW
SCL clock “L” time
4.7
1.3
t
HIGH
SCL clock “H” time
4.0
0.6
t
HD;STA
Hold time for a (repeated)
4.0
0.6
start condition
t
SU;STO
Set-up time for a stop
4.0
0.6
condition
t
SU;STA
Set-up time for a repeated
4.7
0.6
start condition
t
SU;DAT
Data set-up time
250
100
t
HDH;DAT
“H” Data hold time
0
0
t
HDL;DAT
“L” Data hold time
35
35
t
PL;DAT
SDA low stable time after
2.0
0.9
falling of SCL
t
PZ;DAT
SDA off stable time after
2.0
0.9
falling of SCL
t
R
Rising time of SCL and
1000
300
SDA (input)
t
F
Falling time of SCL and
300
300
SDA (input)
t
SP
Pulse width of spikes which
50
50
must be suppressed by the
input Filter
S
Sr
P
Unit
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns
ns
SCL
t
LOW
t
HIGH
t
HD;STA
t
SP
SDA(IN)
t
HD;STA
t
SU;DAT
t
HDL;DAT
t
SU;STA
t
HDH;DAT
t
SU;STO
SDA(OUT)
t
PL;DAT
S
Sr
t
PZ;DAT
P
Start Condition
Repeated Start condition
Stop Condition
*For detailed information refer to ”sOperation 1.2. I
2
C-BUS
transmission system”
-5-
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