IS61C5128AL/AS
IS64C5128AL/AS
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
HIGH SPEED: (IS61/64C5128AL)
• High-speed access time: 10ns, 12 ns
• Low Active Power: 150 mW (typical)
• Low Standby Power: 10 mW (typical)
CMOS standby
LOW POWER: (IS61/64C5128AS)
• High-speed access time: 25ns
• Low Active Power: 75 mW (typical)
• Low Standby Power: 1 mW (typical)
CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Available in 36-pin SOJ (400-mil), 32-pin
sTSOP-I, 32-pin SOP, 44-pin TSOP-II and 32-pin
TSOP-II packages
• Commercial, Industrial and Automotive tempera-
ture ranges available
• Lead-free available
DECEMBER 2013
DESCRIPTION
The
ISSI
IS61C5128AL/AS and IS64C5128AL/AS are high-
speed,
4,194,304-bit
static RAMs organized as 524,288
words by 8 bits. They are fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE. The
active LOW
Write Enable (WE)
controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61C5128AL/AS and IS64C5128AL/AS are packaged
in the JEDEC standard 36-pin SOJ (400-mil), 32-pin sTSOP-I,
32-pin SOP, 44-pin TSOP-II and 32-pin TSOP-II packages
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
V
DD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
12/18/2013
1
IS61C5128AL/AS
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
IS64C5128AL/AS
I/O PIN
V
DD
Current
i
sb
1
, i
sb
2
i
CC
1
, i
CC
2
i
CC
1
, i
CC
2
i
CC
1
, i
CC
2
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O0-I/O7
High-Z
High-Z
d
out
d
in
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
term
t
stg
P
t
i
out
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
in
C
out
Parameter
Input Capacitance
Output Capacitance
Conditions
V
in
= 0V
V
out
= 0V
Max.
5
7
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a
= 25°C,
f = 1 MHz, V
dd
= 5.0V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
oh
V
ol
V
ih
V
il
i
li
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Test Conditions
V
dd
=
Min.,
i
oh
=
–4.0 mA
V
dd
=
Min.,
i
ol
=
8.0 mA
GND
≤
V
in
≤
V
dd
GND
≤
V
out
≤
V
dd
Outputs Disabled
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Min.
2.4
—
2.2
–0.3
–1
–2
–5
–1
–2
–5
Max.
—
0.4
V
dd
+ 0.5
0.8
1
2
5
1
2
5
Unit
V
V
V
V
µA
i
lo
Output Leakage
µA
Note:
1.
V
il
= –3.0V
for pulse width less than 10 ns.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
12/18/2013
综合技术交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
