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IS61NLP51236-200B3LI-TR: 产品描述sram 18mb 512kx36 200mhz sync sram 3.3v; 产品类别半导体其他集成电路（IC）; 文件大小582KB，共37页; 制造商All Sensors; 标准

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IS61NLP51236-200B3LI-TR概述

sram 18mb 512kx36 200mhz sync sram 3.3v

IS61NLP51236-200B3LI-TR规格参数

参数名称	属性值
Manufacture	ISSI
产品种类 Product Category	SRAM
RoHS	Yes
Memory Size	18 Mbi
Organizati	512 k x 36
Access Time	3.1 ns
Interface	Parallel
电源电压-最大 Supply Voltage - Max	3.465 V
Supply Voltage - Mi	3.135 V
Maximum Operating Curre	475 mA
最大工作温度 Maximum Operating Temperature	+ 85 C
最小工作温度 Minimum Operating Temperature	- 40 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	PBGA-165
系列 Packaging	Reel
Maximum Clock Frequency	200 MHz
工厂包装数量 Factory Pack Quantity	2000
类型 Type	Synchronous

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IS61NLP25672/IS61NVP25672

IS61NLP51236/IS61NVP51236

IS61NLP102418/IS61NVP102418

256K x 72, 512K x 36 and 1M x 18

18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

SEPTEMBER 2011

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

DESCRIPTION

The 18 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device

for networking and communications applications. They

are organized as 256K words by 72 bits, 512K words

by 36 bits and 1M words by 18 bits, fabricated with

ISSI

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

• Interleaved or linear burst sequence control us-

ing MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball

PBGA and 209-ball (x72) PBGA packages

• Power supply:

NVP: V

2.5V (± 5%), V

ddq

2.5V (± 5%)

NLP: V

3.3V (± 5%), V

ddq

3.3V/2.5V (± 5%)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

• Leaded option available upon request

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-250

2.6

250

-200

3.1

200

Units

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com

Rev. O

09/19/2011