IS42/45R86400D/16320D/32160D
IS42/45S86400D/16320D/32160D
16Mx32, 32Mx16, 64Mx8
512Mb SDRAM
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply: V
dd
/V
ddq
= 2.3V-3.6V
IS42/45SxxxxxD - V
dd
/V
ddq
=
3.3V
IS42/45RxxxxxD - V
dd
/V
ddq
=
2.5
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Packages:
x8/x16: 54-pin TSOP-II, 54-ball TF-BGA (x16 only)
x32: 90-ball TF-BGA
• Temperature Range:
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
Automotive, A1 (-40
o
C to +85
o
C)
Automotive, A2 (-40
o
C to +105
o
C)
SEPTEMBER 2012
DEVICE OVERVIEW
ISSI
's 512Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 512Mb SDRAM is organized as follows.
PACKAGE INFORMATION
IS42/45S32160D IS42/45S16320D IS42/45S86400D
IS42/45R32160D IS42/45R16320D IS42/45R86400D
4M x 32 x 4
banks
90-ball TF-BGA
8M x 16 x 4
banks
54-pin TSOP-II
54-ball TF-BGA
16M x 8 x 4
banks
54-pin TSOP-II
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-5
5
10
200
100
5.0
6
-6
6
10
167
100
5.4
6
-7
7
7.5
143
133
5.4
5.4
Unit
ns
ns
Mhz
Mhz
ns
ns
ADDRESS TABLE
16M x 32
4M x 32 x 4
banks
Bank Address BA0, BA1
Pins
Autoprecharge A10/AP
Pins
Row Address 8K(A0 – A12)
Column
512(A0 – A8)
Address
Refresh Count
Com./Ind./A1 8K / 64ms
A2
8K / 16ms
Parameter
Configuration
32M x 16
8M x 16 x 4
banks
BA0, BA1
A10/AP
64M x 8
16M x 8 x 4
banks
BA0, BA1
A10/AP
8K(A0 – A12) 8K(A0 – A12)
1K(A0 – A9)
2K(A0 – A9,
A11)
8K / 64ms
8K / 16ms
8K / 64ms
8K / 16ms
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
08/29/2012
1
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D
DEVICE OVERVIEW
The 512Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in either 3.3V
V
dd
/V
ddq
or 2.5V V
dd
/V
ddq
memory systems, depending
on the DRAM option. Internally configured as a quad-bank
DRAM with a synchronous interface.
The 512Mb SDRAM (536,870,912 bits) includes an AUTO
REFRESH MODE, and a power-saving, power-down
mode. All signals are registered on the positive edge of
the clock signal, CLK. All inputs and outputs are LVTTL
compatible.
The 512Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A12 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 8MX16X4
BANKS SHOWN)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
16
2
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
MODE
REGISTER
13
REFRESH
CONTROLLER
DQ 0-15
SELF
REFRESH
CONTROLLER
A10
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
16
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
16
REFRESH
COUNTER
8192
8192
8192
8192
ROW DECODER
MULTIPLEXER
13
MEMORY CELL
ARRAY
13
ROW
ADDRESS
LATCH
13
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
10
1024
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
10
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
08/29/2012
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
A0-A12
A0-A9, A11
BA0, BA1
DQ0 to DQ7
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
Data Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
08/29/2012
3
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
V
DD
DQML
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
V
SS
NC
DQMH
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
A0-A12
A0-A9
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQML
DQMH
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
x16 Lower Byte, Input/Output Mask
x16 Upper Byte, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
08/29/2012
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D
PIN CONFIGURATION
54-ball TF-BGA for x16
(Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
package code: B
1
2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8
NC
VSS
CKE
A9
A6
A4
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS
BA0
A0
A3
RAS
BA1
A1
A2
WE
CS
A10
VDD
DQMH CLK
A12
A8
VSS
A11
A7
A5
PIN DESCRIPTIONS
A0-A12
A0-A9
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQML
DQMH
V
dd
Vss
V
ddq
V
ssq
NC
Write Enable
x16 Lower Byte Input/Output Mask
x16 Upper Byte Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
08/29/2012
5
FPGA/CPLD
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