IS43/46DR16160B
16Mx16 DDR2 DRAM
FEATURES
DESCRIPTION
• V
dd
= 1.8V ±0.1V, V
ddq
= 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers per
clock cycle
• Differential data strobe (DQS,
DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions with
CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, 6 and 7 sup-
ported
• Posted CAS and programmable additive latency (AL)
0, 1, 2, 3, 4, 5 and 6 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and re-
duced strength options
• On-die termination (ODT)
SEPTEMBER 2013
ISSI's 256Mb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
ADDRESS TABLE
Parameter
Configuration
Refresh Count
Row Addressing
Column
Addressing
Bank Addressing
Precharge
Addressing
16M x 16
4M x 16 x 4
banks
8K/64ms
8K (A0-A12)
512 (A0-A8)
BA0, BA1
A10
OPTIONS
• Configuration:
16Mx16 (4Mx16x4 banks) IS43/46DR16160B
• Package:
84-ball TW-BGA (8mm x 12.5mm)
Timing – Cycle time
2.5ns @CL=5 DDR2-800D
2.5ns @CL=6 DDR2-800E
3.0ns @CL=5 DDR2-667D
3.75ns @CL=4 DDR2-533C
5.0ns @CL=3 DDR2-400B
• Temperature Range:
Commercial (0°C
≤
Tc
≤
85°C)
Industrial (-40°C
≤
Tc
≤
95°C; -40°C
≤
T
a
≤
85°C)
Automotive, A1 (-40°C
≤
Tc
≤
95°C; -40°C
≤
T
a
≤
85°C)
Automotive, A2 (-40°C
≤
Tc; T
a
≤
105°C)
Tc = Case Temp, T
a
= Ambient Temp
KEY TIMING PARAMETERS
Speed Grade
tRCD
tRP
tRC
tRAS
tCK @CL=3
tCK @CL=4
tCK @CL=5
tCK @CL=6
-25D
12.5
12.5
55
40
5
3.75
2.5
2.5
-3D
15
15
55
40
5
3.75
3
—
-37C
15
15
55
40
5
3.75
—
—
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
9/6/2013
1
IS43/46DR16160B
GENERAL DESCRIPTION
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the active
command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12 select the row). The
address bits registered coincident with the Read or Write command are used to select the starting column location
(A0-A8) for the burst access and to determine if the auto precharge A10 command is to be issued. Prior to normal
operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
FUNCTIONAL BLOCK DIAGRAM
DMa - DMb
Notes:
1. An:n = no. of address pins - 1
2. DQm: m = no. of data pins - 1
3. DMa - DMb = UDM, LDM; DQSa - DQSb = UDQS, LDQS;
DQSa
-
DQSb
=
UDQS, LDQS
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
9/6/2013
IS43/46DR16160B
PIN DESCRIPTION TABLE
Symbol
CK,
CK
Type
Input
Function
Clock: CK and
CK
are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of
CK.
Output (read) data is referenced to the crossings of CK and
CK
(both directions of
crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE LOW provides Precharge
Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. After VREF has become
stable during the power on and initialization sequence, it must be maintained for
proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must be maintained to this input. CKE must be maintained HIGH throughout read and
write accesses. Input buffers, excluding CK,
CK,
ODT and CKE are disabled during
power-down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when
CS
is registered HIGH.
CS
provides for
external Rank selection on systems with multiple Ranks.
CS
is considered part of the
command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal
to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS,
DQS,
DM
signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT.
Command Inputs:
RAS, CAS
and
WE
(along with
CS)
define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines if the mode
register or one of the extended mode registers is to be accessed during a MRS or
EMRS command cycle.
Address Inputs: Provide the row address for Active commands and the column
address and Auto Precharge bit for Read/Write commands to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0 -
BA1. The address inputs also provide the op-code during MRS or EMRS commands.
CKE
Input
CS
Input
ODT
RAS, CAS, WE
Input
Input
UDM, LDM
Input
BA0 - BA1
Input
A0 - A12
Input
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
9/6/2013
3
IS43/46DR16160B
Symbol
DQ0-15
Type
Input/
Output
Function
Data Input/Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobes DQS(n) may be used in single ended mode
or paired with optional complementary signals
DQS(n)
to provide differential pair
signaling to the system during both reads and writes. A control bit at EMR(1)[A10]
enables or disables all complementary data strobe signals.
UDQS, (UDQS),
LDQS, (LDQS)
Input/
Output
LDQS corresponds to the data on DQ0-DQ7
UDQS corresponds to the data on DQ8-DQ15
NC
VDDQ
VSSQ
VDDL
VSSDL
VDD
VSS
VREF
Supply
Supply
Supply
Supply
Supply
Supply
Supply
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.8 V +/- 0.1 V
DQ Ground
DLL Power Supply: 1.8 V +/- 0.1 V
DLL Ground
Power Supply: 1.8 V +/- 0.1 V
Ground
Reference voltage
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
9/6/2013
IS43/46DR16160B
PIN CONFIGURATION
PACKAGE CODE: B 84 BALL FBGA (Top View) (8 mm x 12.5 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VDD
NC
VSS
VSSQ
UDQS
VDDQ
UDQS VSSQ DQ15
VDDQ DQ8 VDDQ
DQ10 VSSQ DQ13
VSSQ
LDQS
VDDQ
LDQS VSSQ DQ7
VDDQ DQ0 VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
VSSQ DQ5
CK
CK
CS
A0
A4
A8
NC
VSS
VDD
VDD
ODT
DQ14 VSSQ UDM
VDDQ DQ9 VDDQ
DQ12 VSSQ DQ11
VDD
DQ6
NC
VSS
VSSQ LDM
VDDQ DQ1 VDDQ
DQ4
VSSQ DQ3
VSS
WE
BA1
VDDL VREF
CKE
NC
BA0
A10/AP A1
VSS
A3
A7
VDD
A12
A5
A9
NC
Not populated
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ15
LDQS, UDQS
/LDQS, /UDQS
/CS
CKE
CK, /CK
LDM to UDM
Rev. A
9/6/2013
Function
Address inputs
Bank select
Data input/output
Differential data strobe
Chip select
Clock enable
Differential clock input
Write data mask
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
5
/RAS, /CAS, /WE Command input
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