IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
256K x 72, 512K x 36 and 1M x 18
18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
SEPTEMBER 2011
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
DESCRIPTION
The 18 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device
for networking and communications applications. They
are organized as 256K words by 72 bits, 512K words
by 36 bits and 1M words by 18 bits, fabricated with
ISSI
's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
•
CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball
PBGA and 209-ball (x72) PBGA packages
• Power supply:
NVP: V
dd
2.5V (± 5%), V
ddq
2.5V (± 5%)
NLP: V
dd
3.3V (± 5%), V
ddq
3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
• Leaded option available upon request
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
-250
2.6
4
250
-200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. O
09/19/2011
1
IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
PIN CONFIgURATION 256K x 72, 209-Ball PBgA (TOP VIEW)
—
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
2
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
3
A
BWc
BWh
V
SS
V
ddq
V
SS
V
ddq
V
SS
V
ddq
CLK
V
ddq
V
SS
V
ddq
V
SS
V
ddq
V
SS
NC
A
TMS
4
CE2
BWg
BWd
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
A
A
TDI
5
A
NC
NC
NC
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
NC
NC
A
A
6
ADV
WE
CE
OE
V
dd
NC
NC
NC
NC
CKE
NC
NC
NC
ZZ
V
dd
MODE
A
A1
A0
7
A
A
NC
NC
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
NC
NC
A
A
8
CE2
BWb
BWe
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
A
A
TDO
9
A
BWf
BWa
V
SS
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
11 x 19 Ball BGA—14 x 22 mm
2
Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
A0, A1
Pin Name
Synchronous Address Inputs
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
ADV
Synchronous Burst Address Advance
BWa-BWh
Synchronous Byte Write Enable
CE, CE2, CE2
Synchronous Chip Enable
CLK
Synchronous Clock
CKE
Clock Enable
DQx
Synchronous Data Input/Output
DQPx
Parity Data I/O
V
SS
MODE
OE
TCK, TDI
TDO, TMS
V
dd
V
ddq
WE
ZZ
Ground
Burst Sequence Selection
Output Enable
JTAG Pins
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Write Enable
Snooze Enable
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. O
09/19/2011
FPGA/CPLD
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