MR4A08B
FEATURES
•
+3.3 Volt power supply
•
Fast 35 ns read/write cycle
•
SRAM compatible timing
•
Unlimited read & write endurance
•
Data always non-volatile for >20-years at temperature
•
RoHS-compliant small footprint BGA and TSOP2 packages
2M x 8 MRAM Memory
BENEFITS
•
One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems
for simpler, more efficient designs
•
Improves reliability by replacing battery-backed SRAM
INTRODUCTION
The
MR4A08B
is a 16,777,216-bit magnetoresistive random access
memory (MRAM) device organized as 2,097,152 words of 8 bits.
The MR4A08B offers SRAM compatible 35ns read/write timing with
unlimited endurance. Data is always non-volatile for greater than
20-years. Data is automatically protected on power loss by low-
voltage inhibit circuitry to prevent writes with voltage out of specification. The
MR4A08B is the ideal memory solution for applications that must permanently store and retrieve critical
data and programs quickly.
The
MR4A08B
is available in small footprint 400-mil, 44-lead plastic small-outline TSOP type-II package or
10 mm x 10 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are com-
patible with similar low-power SRAM products and other non-volatile RAM products.
The
MR4A08B
provides highly reliable data storage over a wide range of temperatures. The product is of-
fered with commercial (0 to +70 °C) and industrial (-40 to +85 °C) operating temperature range options.
RoHS
CONTENTS
1. DEVICE PIN ASSIGNMENT......................................................................... 2
2. ELECTRICAL SPECIFICATIONS................................................................. 4
3. TIMING SPECIFICATIONS.......................................................................... 7
4. ORDERING INFORMATION....................................................................... 11
5. MECHANICAL DRAWING.......................................................................... 12
6. REVISION HISTORY...................................................................................... 14
How to Reach Us.......................................................................................... 14
Copyright © Everspin Technologies 2014
1
MR4A08B Rev. 7 4/2014
MR4A08B
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
G
OUTPUT
ENABLE
BUFFER
10
11
ROW
DECODER
COLUMN
DECODER
OUTPUT ENABLE
A[20:0]
21
ADDRESS
BUFFER
E
CHIP
ENABLE
BUFFER
2M x 8 BIT
MEMORY
ARRAY
8
SENSE
AMPS
8
OUTPUT
BUFFER
8
W
WRITE
ENABLE
BUFFER
8
FINAL
WRITE
DRIVERS
8
WRITE
DRIVER
8
DQ[7:0]
WRITE ENABLE
Table 1.1 Pin Functions
Signal Name
A
E
W
G
DQ
V
DD
V
SS
DC
NC
Function
Address Input
Chip Enable
Write Enable
Output Enable
Data I/O
Power Supply
Ground
Do Not Connect
No Connection
Copyright © Everspin Technologies 2014
2
MR4A08B Rev. 7 4/2014
DEVICE PIN ASSIGNMENT
MR4A08B
Figure 1.2 Pin Diagrams for Available Packages (Top View)
DC
A
20
A
A
A
A
A
E
V
DD
V
SS
W
A
A
A
A
A
DC
DC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DC
A
19
DC
A
A
A
A
G
1
DC
NC
DQ
2
G
DC
NC
DQ
DQ
3
A
A
A
4
A
A
A
A
5
A
E
NC
DQ
DQ
6
DC
DC
DQ
A
B
C
D
E
F
G
H
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
DQ
DC
DC
A
A
A
A
A
DC
DC
DQ
3
NC
20
NC
A
A
A
A
W
A
NC
NC
A
19
44 Pin TSOP2
48 Pin FBGA
Table 1.2 Operating Modes
E
1
H
L
L
L
1
2
G
1
X
H
L
X
W
1
X
H
H
L
Mode
Not selected
Output disabled
Byte Read
Byte Write
V
DD
Current
I
SB1
, I
SB2
I
DDR
I
DDR
I
DDW
DQ[7:0]
2
Hi-Z
Hi-Z
D
Out
D
in
H = high, L = low, X = don’t care
Hi-Z = high impedance
Copyright © Everspin Technologies 2014
3
MR4A08B Rev. 7 4/2014
MR4A08B
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any
voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken
to avoid application of any magnetic field more intense than the maximum field intensity specified
in the maximum ratings.
Table 2.1 Absolute Maximum Ratings
1
Parameter
Supply voltage
2
Voltage on any pin
2
Output current per pin
Package power dissipation
3
Temperature under bias
MR4A08B (Commercial)
MR4A08BC (Industrial)
Symbol
V
DD
V
IN
I
OUT
P
D
T
BIAS
T
stg
T
Lead
H
max_write
H
max_read
Value
-0.5 to 4.0
-0.5 to V
DD
+
0.5
±20
0.600
-10 to 85
-45 to 95
-55 to 150
260
8000
8000
Unit
V
V
mA
W
°C
°C
°C
A/m
A/m
Storage Temperature
Lead temperature during solder (3 minute max)
Maximum magnetic field during write
MR4A08B (All Temperatures)
Maximum magnetic field during read or standby
1
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-
tion should be restricted to recommended operating conditions. Exposure to excessive voltages or
magnetic fields could affect device reliability.
All voltages are referenced to V
SS
.
Power dissipation capability depends on package characteristics and use environment.
2
3
Copyright © Everspin Technologies 2014
4
MR4A08B Rev. 7 4/2014
Electrical Specifications
Table 2.2 Operating Conditions
Parameter
Power supply voltage
Write inhibit voltage
Input high voltage
Input low voltage
Temperature under bias
MR4A08B (Commercial)
MR4A08BC (Industrial)
1.
2.
3.
MR4A08B
Symbol
V
DD
V
WI
V
IH
V
IL
T
A
Min
3.0
1
2.5
2.2
-0.5
3
0
-40
Typical
3.3
2.7
-
-
Max
3.6
3.0
1
V
DD
+ 0.3
2
0.8
70
85
Unit
V
V
V
V
°C
There is a 2 ms startup time once V
DD
exceeds V
DD,
(min). See
Power Up and Power Down Sequencing
below.
V
IH
(max) = V
DD
+ 0.3 V
DC
; V
IH
(max) = V
DD
+ 2.0 V
AC
(pulse width ≤ 10 ns) for I ≤ 20.0 mA.
V
IL
(min) = -0.5 V
DC
; V
IL
(min) = -2.0 V
AC
(pulse width ≤ 10 ns) for I ≤ 20.0 mA.
Power Up and Power Down Sequencing
MRAM is protected from write operations whenever V
DD
is less than V
WI
. As soon as V
DD
exceeds V
DD
(min),
there is a startup time of 2 ms before read or write operations can start. This time allows memory power
supplies to stabilize.
The E and W control signals should track V
DD
on power up to V
DD
- 0.2 V or V
IH
(whichever is lower) and re-
main high for the startup time. In most systems, this means that these signals should be pulled up with a
resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and
W should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where V
DD
goes below V
WI
, writes are protected and a startup time must be
observed when power returns above V
DD
(min).
Figure 2.1 Power Up and Power Down Diagram
V
WIDD
V
DD
2 ms
READ/WRITE
INHIBITED
NORMAL
OPERATION
2 ms
RECOVER
NORMAL
OPERATION
STARTUP
BROWNOUT or POWER LOSS
READ/WRITE
INHIBITED
V
IH
V
IH
E
W
Copyright © Everspin Technologies 2014
5
MR4A08B Rev. 7 4/2014
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