IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
128K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 35ns, 45ns, 55ns
• CMOS low power operation:
12 mW (typical) operating
4 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply:
1.65V--2.2V V
dd
(62WV1288dALL)
2.3V--3.6V V
dd
(62WV1288dBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and automotive temperature support
• Lead-free available
DECEMBER 2010
are high-speed, 1M bit static RAMs organized as
128K words by 8 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. his highly reliable process
T
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
DESCRIPTION
The
ISSI
IS62/65WV1288DALL and IS62/65WV1288DBLL
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected), the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62/65WV1288DALL and IS62/65WV1288DBLL are
packaged in the JEDEC standard 32-pin TSOP (TYPEI),
sTSOP (TYPEI), SOP, and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 8
MEMORY ARRAY
V
DD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CS2
CS1
OE
WE
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
CONTROL
CIRCUIT
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
1
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
X
H
H
L
CS1
H
X
L
L
L
CS2
X
L
H
H
H
OE
X
X
H
L
X
I
/O Operation
High-Z
High-Z
High-Z
d
Out
d
in
V
DD
Current
i
sB
1
, i
sB
2
i
sB
1
, i
sB
2
i
CC
i
CC
i
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
term
V
dd
t
stg
P
t
Parameter
Terminal Voltage with Respect to GND
V
dd
Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to V
dd
+ 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
in
C
i/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
in
= 0V
V
Out
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C,
f = 1 MHz, V
dd
= 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
3
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 3.3V + 5%
Symbol
V
Oh
V
OL
V
ih
V
iL
i
Li
i
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
dd
=
Min., i
Oh
=
–1 mA
V
dd
=
Min., i
OL
=
2.1 mA
GND ≤ V
in
≤
V
dd
GND ≤ V
Out
≤
V
dd
,
Outputs Disabled
Min.
2.4
—
2
–0.3
–1
–1
Max.
—
0.4
V
dd
+ 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Note:
1. V
iL
(min.) = –0.3V DC; V
iL
(min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
V
ih
(max.) = V
dd
+ 0.3V
dC; V
ih
(max.) = V
dd
+ 2.0V
AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 2.3V-3.6V
Symbol Parameter
V
Oh
V
OL
V
ih
V
iL
i
Li
i
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
dd
=
Min., i
Oh
=
–1.0 mA
V
dd
=
Min., i
OL
=
2.1 mA
GND ≤
V
in
≤
V
dd
GND ≤
V
Out
≤
V
dd
,
Outputs Disabled
Min.
1.8
—
2.0
–0.3
–1
–1
Max.
—
0.4
V
dd
+ 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Note:
1.
V
iL
(min.) = –0.3V DC; V
iL
(min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
V
ih
(max.) = V
dd
+ 0.3V
dC; V
ih
(max.) = V
dd
+ 2.0V
AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 1.65V-2.2V
Symbol Parameter
V
Oh
Output HIGH Voltage
V
OL
V
ih
V
iL
(1)
i
Li
i
LO
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
i
Oh
=
-0.1 mA
V
DD
1.65-2.2V
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
V
dd
+ 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
i
OL
=
0.1 mA
1.65-2.2V
1.65-2.2V
1.65-2.2V
GND ≤
V
in
≤
V
dd
GND ≤
V
Out
≤
V
dd
,
Outputs Disabled
Note:
1.
V
iL
(min.) = –0.3V DC; V
iL
(min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
V
ih
(max.) = V
dd
+ 0.3V
dC; V
ih
(max.) = V
dd
+ 2.0V
AC (pulse width < 10 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
