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IS61NLP12836EC-200B3LI: 产品描述sram 4mb, 200mhz, 3.3v 128k x 36 sync sram; 产品类别半导体其他集成电路（IC）; 文件大小2MB，共40页; 制造商All Sensors; 标准

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IS61NLP12836EC-200B3LI在线购买

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IS61NLP12836EC-200B3LI概述

sram 4mb, 200mhz, 3.3v 128k x 36 sync sram

IS61NLP12836EC-200B3LI规格参数

参数名称	属性值
Manufacture	ISSI
产品种类 Product Category	SRAM
RoHS	Yes
Memory Size	4 Mbi
Organizati	128 k x 36
Access Time	3.1 ns
电源电压-最大 Supply Voltage - Max	3.465 V
Supply Voltage - Mi	3.135 V
Maximum Operating Curre	210 mA
最大工作温度 Maximum Operating Temperature	+ 85 C
最小工作温度 Minimum Operating Temperature	- 40 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	BGA-165
Maximum Clock Frequency	200 MHz
Memory Type	Synchronous SRAM

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IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC

IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE 'NO WAIT' STATE

BUS SYNCHRONOUS SRAM

MARCH 2014

FEATURES

•

100 percent bus utilization

•

No wait cycles between Read and Write

•

Internal self-timed write cycle

•

Individual Byte Write Control

•

Single R/W (Read/Write) control pin

•

Clock controlled, registered address, data and

control

•

Interleaved or linear burst sequence control

using MODE input

•

Three chip enables for simple depth

expansion and address pipelining

•

Power Down mode

•

Common data inputs and data outputs

•

/CKE pin to enable clock and suspend

operation

•

JEDEC 100-pin QFP, 165-ball BGA and 119-

ball BGA packages

•

Power supply:

NLP: V

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

NVP: V

2.5V (± 5%), V

DDQ

2.5V (± 5%)

•

JTAG Boundary Scan for BGA packages

•

Industrial and Automotive temperature support

•

Lead-free available

•

Error Detection and Error Correction

DESCRIPTION

The 4Mb product family features high-speed, low-

power synchronous static RAMs designed to

provide a burstable, high-performance, 'no wait'

state, device for networking and communications

applications. They are organized as 128K words

by 36 bits and 256K words by 18 bits, fabricated

with

ISSI's

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles

are eliminated when the bus switches from read

to write, or write to read. This device integrates a

2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single

monolithic circuit.

All synchronous inputs pass through registers are

controlled by a positive-edge-triggered single

clock input. Operations may be suspended and all

synchronous inputs ignored when Clock Enable,

/CKE is HIGH. In this state the internal device will

hold their previous values.

All Read, Write and Deselect cycles are initiated

by the ADV input. When the ADV is HIGH the

internal burst counter is incremented. New

external addresses can be loaded when ADV is

LOW.

Write cycles are internally self-timed and are

initiated by the rising edge of the clock inputs and

when /WE is LOW. Separate byte enables allow

individual bytes to be written.

A burst mode pin (MODE) defines the order of the

burst sequence. When tied HIGH, the interleaved

burst sequence is selected. When tied LOW, the

linear burst sequence is selected

250

2.6

250

200

3.1

200

Units

MHz

FAST ACCESS TIME

Symbol

MAX

Parameter

Clock Access Time

Cycle time

Frequency

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. C

03/6/2014

IS61NLP12836EC-200B3LI相似产品对比

	IS61NLP12836EC-200B3LI	IS61NLP12836EC-200B3LI-TR
描述	sram 4mb, 200mhz, 3.3v 128k x 36 sync sram	sram 4mb, 200mhz, 3.3v 128k x 36 sync sram
Manufacture	ISSI	ISSI
产品种类 Product Category	SRAM	SRAM
RoHS	Yes	Yes
Memory Size	4 Mbi	4 Mbi
Organizati	128 k x 36	128 k x 36
Access Time	3.1 ns	3.1 ns
电源电压-最大 Supply Voltage - Max	3.465 V	3.465 V
Supply Voltage - Mi	3.135 V	3.135 V
Maximum Operating Curre	210 mA	210 mA
最大工作温度 Maximum Operating Temperature	+ 85 C	+ 85 C
最小工作温度 Minimum Operating Temperature	- 40 C	- 40 C
安装风格 Mounting Style	SMD/SMT	SMD/SMT
封装 / 箱体 Package / Case	BGA-165	BGA-165
Maximum Clock Frequency	200 MHz	200 MHz
Memory Type	Synchronous SRAM	Synchronous SRAM

IS61NLP12836EC-200B3LI

IS61NLP12836EC-200B3LI在线购买

IS61NLP12836EC-200B3LI概述

IS61NLP12836EC-200B3LI规格参数

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IS61NLP12836EC-200B3LI相似产品对比

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