IS61NLP12832B

IS61NLP12836B/IS61NVP12836B

IS61NLP25618A/IS61NVP25618A

128K x 32, 128K x 36, and 256K x 18

4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

SEPTEMBER 2007

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

DESCRIPTION

The 4 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 128K words by 32 bits, 128K words by 36

bits, and 256K words by 18 bits, fabricated with

ISSI

's

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

Write cycles are internally self-timed and are initiated

by the rising edge of the clock inputs and when

WE

is

LOW. Separate byte enables allow individual bytes to be

written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

• Interleaved or linear burst sequence control us-

ing MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE

pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

• Power supply:

NVP: V

dd

2.5V (± 5%), V

ddq

2.5V (± 5%)

NLP: V

dd

3.3V (± 5%), V

ddq

3.3V/2.5V (± 5%)

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

t

kq

t

kc

Parameter

Clock Access Time

Cycle Time

Frequency

-250

2.6

4

250

-200

3.1

5

200

Units

ns

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

09/10/07

1

IS61NLP12832B

IS61NLP12836B/IS61NVP12836B

IS61NLP25618A/IS61NVP25618A

BLOCK DIAGRAM

x 32/x 36: A [0:16] or

x 18: A [0:17]

ADDRESS

REGISTER

A2-A16 or A2-A17

128Kx32;

128Kx36;

256Kx18

MEMORY ARRAY

K

DATA-IN

REGISTER

MODE

A0-A1

BURST

ADDRESS

COUNTER

A'0-A'1

CLK

CKE

CONTROL

LOGIC

K

WRITE

ADDRESS

REGISTER

WRITE

ADDRESS

REGISTER

K

DATA-IN

REGISTER

CE

CE2

ADV

WE

BWŸ

X

OE

ZZ

DQx/DQPx

}

CONTROL

REGISTER

CONTROL

LOGIC

K

OUTPUT

REGISTER

BUFFER

(X=a,b,c,d or a,b)

32, 36 or 18

2

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

09/10/07

IS61NLP12832B

IS61NLP12836B/IS61NVP12836B

IS61NLP25618A/IS61NVP25618A

165-Ball, 13 mm x 15mm BGA

1 mm Ball Pitch, 11 x 15 Ball Array

Bottom View

119-Ball, 14 mm x 22 mm BGA

1 mm Ball Pitch, 7 x 17 Ball Array

Bottom View

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

09/10/07

3

IS61NLP12832B

IS61NLP12836B/IS61NVP12836B

IS61NLP25618A/IS61NVP25618A

PIN CONFIgURATION — 128K

x

36, 165-Ball PBgA (TOP VIEW)

1

2

3

4

5

6

7

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

NC

DQPc

DQc

NC

DQd

DQPd

NC

MODE

A

NC

DQc

NC

DQd

NC

CE

CE2

V

ddq

V

ddq

V

ddq

V

ddq

V

ddq

NC

V

ddq

V

ddq

V

ddq

V

ddq

V

ddq

A

BWc

BWd

V

SS

V

dd

V

dd

V

dd

V

dd

V

dd

V

dd

V

dd

V

dd

V

dd

V

SS

A

BWb

BWa

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

CE2

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1*

A0*

CKE

WE

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

8

OE

V

SS

V

dd

V

dd

V

dd

V

dd

V

dd

V

dd

V

dd

V

dd

V

dd

V

SS

A

9

NC

V

ddq

V

ddq

V

ddq

V

ddq

V

ddq

NC

V

ddq

V

ddq

V

ddq

V

ddq

V

ddq

A

10

A

NC

DQb

NC

DQa

NC

A

11

NC

DQPb

DQb

ZZ

DQa

DQPa

NC

A

ADV

Note:

A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

A

A0, A1

ADV

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address Advance/

Load

WE

Synchronous Read/Write Control

Input

CLK

Synchronous Clock

CKE

Clock Enable

CE, CE2,

CE2 Synchronous Chip Enable

BWx (x=a-d)

Synchronous Byte Write Inputs

OE

Output Enable

ZZ

Power Sleep Mode

MODE

V

DD

NC

DQx

DQPx

V

DDQ

V

SS

Burst Sequence Selection

3.3V/2.5V Power Supply

No Connect

Data Inputs/Outputs

Parity Data I/O

Isolated output Power Supply

3.3V/2.5V

Ground

4

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

09/10/07

IS61NLP12832B

IS61NLP12836B/IS61NVP12836B

IS61NLP25618A/IS61NVP25618A

119-PIN

PBgA PACKAgE

CONFIGURATION

1

2

3

128K x 36 (TOP VIEW)

4

5

6

7

A

B

C

D

E

F

V

DDQ

NC

DQc

V

DDQ

DQc

V

DDQ

DQd

V

DDQ

DQd

NC

V

DDQ

A

CE2

A

DQPc

DQc

V

DD

DQd

DQPd

A

NC

A

V

SS

V

SS

V

SS

BWc

V

SS

NC

V

SS

BWd

V

SS

V

SS

V

SS

MODE

A

NC

ADV

V

DD

NC

CE

OE

NC

WE

V

DD

CLK

NC

CKE

A

1

*

A

0

*

V

DD

A

NC

A

Vss

BWb

Vss

NC

Vss

BWa

Vss

NC

A

NC

A

CE2

A

DQPb

DQb

V

DD

DQa

DQPa

A

NC

V

DDQ

NC

DQb

V

DDQ

DQb

V

DDQ

DQa

V

DDQ

DQa

NC

ZZ

V

DDQ

G

H

J

K

L

M

N

P

R

T

U

Note:

A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

A

A0, A1

ADV

WE

CLK

CKE

CE

CE2

BWx (x=a-d)

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address Advance/

Load

Synchronous Read/Write Control

Input

Synchronous Clock

Clock Enable

Synchronous Chip Select

Synchronous Byte Write Inputs

OE

ZZ

MODE

V

dd

V

SS

NC

DQa-DQd

DQPa-Pd

V

ddq

Output Enable

Power Sleep Mode

Burst Sequence Selection

Power Supply

Ground

No Connect

Data Inputs/Outputs

Parity Data I/O

Output Power Supply

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

09/10/07

5

参数名称	属性值
Manufacture	ISSI
产品种类 Product Category	SRAM
RoHS	Yes
Memory Size	4 Mbi
Access Time	3.1 ns
电源电压-最大 Supply Voltage - Max	3.465 V
Supply Voltage - Mi	3.135 V
Maximum Operating Curre	210 mA
最大工作温度 Maximum Operating Temperature	+ 85 C
最小工作温度 Minimum Operating Temperature	- 40 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	BGA
系列 Packaging	Reel
Maximum Clock Frequency	200 MHz
工厂包装数量 Factory Pack Quantity	1000
类型 Type	Synchronous

	IS61NLP12836B-200B2LI-TR	IS61NLP25618A-200B3LI-TR	IS61NLP12836B-200TQLI-TR	IS61NLP25618A-200B3LI
描述	sram 4mb 128kx36 200mhz sync sram 3.3v	sram 4M (256kx18) 200mhz sync sram 3.3v	sram 4mb 128kx36 200mhz sync sram 3.3v	sram 4M (256kx18) 200mhz sync sram 3.3v
Manufacture	ISSI	ISSI	ISSI	ISSI
产品种类 Product Category	SRAM	SRAM	SRAM	SRAM
RoHS	Yes	Yes	Yes	Yes
Memory Size	4 Mbi	4 Mbi	4 Mbi	4 Mbi
Access Time	3.1 ns	3.1 ns	3.1 ns	3.1 ns
电源电压-最大 Supply Voltage - Max	3.465 V	3.465 V	3.465 V	3.465 V
Supply Voltage - Mi	3.135 V	3.135 V	3.135 V	3.135 V
Maximum Operating Curre	210 mA	210 mA	210 mA	210 mA
最大工作温度 Maximum Operating Temperature	+ 85 C	+ 85 C	+ 85 C	+ 85 C
最小工作温度 Minimum Operating Temperature	- 40 C	- 40 C	- 40 C	- 40 C
安装风格 Mounting Style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
封装 / 箱体 Package / Case	BGA	BGA	TQFP-100	BGA
系列 Packaging	Reel	Reel	Reel	Tray
Maximum Clock Frequency	200 MHz	200 MHz	200 MHz	200 MHz
工厂包装数量 Factory Pack Quantity	1000	2000	800	144
类型 Type	Synchronous	Synchronous	Synchronous	Synchronous

IS61NLP12836B-200B2LI-TR

IS61NLP12836B-200B2LI-TR在线购买

IS61NLP12836B-200B2LI-TR概述

IS61NLP12836B-200B2LI-TR规格参数

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