IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED
SINGLE CYCLE DESELECT STATIC RAM
JULY 2014
FEATURES
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Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
Power supply:
LPS: V
DD
3.3V (± 5%), V
DDQ
3.3V/2.5V (± 5%)
VPS: V
DD
2.5V (± 5%), V
DDQ
2.5V (± 5%)
VVPS: V
DD
1.8V (± 5%), V
DDQ
1.8V (± 5%)
JTAG Boundary Scan for BGA packages
Commercial, Industrial and Automotive
temperature support
Lead-free available
For leaded options, please contact ISSI
DESCRIPTION
The 18Mb product family features high-speed, low-
power synchronous static RAMs designed to provide
burstable, high-performance memory for
communication and networking applications. The
IS61LPS/VPS/VVPS51236B are organized as 524,288
words by 36bits. The IS61LPS/VPS/VVPS102418B are
organized as 1,048,576 words by 18bits. Fabricated
with ISSI's advanced CMOS technology, the device
integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock input. Write cycles can
be one to four bytes wide as controlled by the write
control inputs.
Separate byte enables allow individual bytes to be
written. The byte write operation is performed by using
the byte write enable (/BWE) input combined with one
or more individual byte write signals (/BWx). In
addition, Global Write (/GW) is available for writing all
bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address
Status Processor) or /ADSC (Address Status Cache
Controller) input pins. Subsequent burst addresses can
be generated internally and controlled by the /ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence
order. Linear burst is achieved when this pin is tied
LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
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FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access
Time
Cycle time
Frequency
-250
2.6
4
250
-200
3.0
5
200
Units
ns
ns
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
7/11/2014
1
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