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IS61WV12816BLL-12TLI-TR

产品描述sram 2M 128k x 16, 12ns async sram 3.3v
产品类别半导体    其他集成电路(IC)   
文件大小117KB,共15页
制造商All Sensors
标准  
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IS61WV12816BLL-12TLI-TR概述

sram 2M 128k x 16, 12ns async sram 3.3v

IS61WV12816BLL-12TLI-TR规格参数

参数名称属性值
ManufactureISSI
产品种类
Product Category
SRAM
RoHSYes
Memory Size2 Mbi
Organizati128 k x 16
Access Time12 ns
InterfaceParallel
电源电压-最大
Supply Voltage - Max
3.63 V
Supply Voltage - Mi2.97 V
Maximum Operating Curre40 mA
最大工作温度
Maximum Operating Temperature
+ 85 C
最小工作温度
Minimum Operating Temperature
- 40 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
TSOP II-44
系列
Packaging
Reel
工厂包装数量
Factory Pack Quantity
1000
类型
Type
Asynchronous

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IS61WV12816BLL
IS64WV12816BLL
128K x 16 HIGH-SPEED CMOS STATIC RAM
ISSI
FEBRUARY 2006
®
FEATURES
• High-speed access time:
12 ns: 3.3V + 10%
15 ns: 2.5V-3.6V
• Operating Current: 25mA (typ.)
• Stand by Current: 400µA(typ.)
• TTL and CMOS compatible interface levels
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperatures avail-
able
• Lead-free available
DESCRIPTION
The
ISSI
IS61WV12816BLL and IS64WV12816BLL are
high-speed, 2,097,152-bit static RAM organized as 131,072
words by 16 bits. They are fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV12816BLL and IS64WV12816BLL are packaged
in the JEDEC standard 44-pin TSOP (Type II) and 48-pin
mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128Kx16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
02/03/06
1

 
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