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IS61NLF102418-7.5TQLI-TR: 产品描述sram 18mb, 3.3v, 7.5ns 1mb x 18 sync sram; 产品类别半导体其他集成电路（IC）; 文件大小452KB，共35页; 制造商All Sensors; 标准

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IS61NLF102418-7.5TQLI-TR概述

sram 18mb, 3.3v, 7.5ns 1mb x 18 sync sram

IS61NLF102418-7.5TQLI-TR规格参数

参数名称	属性值
Manufacture	ISSI
产品种类 Product Category	SRAM
Memory Size	18 Mbi
Organizati	1 M x 18
Access Time	7.5 ns
电源电压-最大 Supply Voltage - Max	3.3 V
Supply Voltage - Mi	2.5 V
Maximum Operating Curre	425 mA
最大工作温度 Maximum Operating Temperature	+ 70 C
最小工作温度 Minimum Operating Temperature	0 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	TQFP-100
系列 Packaging	Reel
Maximum Clock Frequency	117 MHz
Memory Type	Synchronous
工厂包装数量 Factory Pack Quantity	800
类型 Type	Synchronous Flow-Through SRAM

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IS61NLF25672/IS61NVF25672

IS61NLF51236/IS61NVF51236

IS61NLF102418/IS61NVF102418

NOVEMBER 2013

256K x 72, 512K x 36 and 1M x 18

18Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

• Clock controlled, registered address,

data and control

DESCRIPTION

The 18 Meg 'NLF/NVF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device

for networking and communications applications. They

are organized as 256K words by 72 bits, 512K words

by 36 bits and 1M words by 18 bits, fabricated with

ISSI

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

WE is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

• Interleaved or linear burst sequence control us-

ing MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE

pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 209-

ball (x72) PBGA packages

• Power supply:

NVF: V

2.5V (± 5%), V

ddq

2.5V (± 5%)

NLF: V

3.3V (± 5%), V

ddq

3.3V/2.5V (± 5%)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

6.5

7.5

133

7.5

8.5

117

Units

MHz

Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-

ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. E

10/25/2013

IS61NLF102418-7.5TQLI-TR相似产品对比

	IS61NLF102418-7.5TQLI-TR	IS61NVF51236-6.5TQL	IS61NLF102418-7.5TQLI	IS61NVF51236-6.5TQL-TR	IS61NLF51236-7.5TQLI	IS61NLF51236-7.5TQLI-TR
描述	sram 18mb, 3.3v, 7.5ns 1mb x 18 sync sram	sram 18mb (512kx36) 6.5ns sync sram 2.5v	sram 18mb, 3.3v, 7.5ns 1mb x 18 sync sram	sram 18mb (512kx36) 6.5ns sync sram 2.5v	sram 18m (512kx36) 7.5ns sync sram 3.3v	sram 18m (512kx36) 7.5ns sync sram 3.3v
Manufacture	ISSI	ISSI	ISSI	ISSI	ISSI	ISSI
产品种类 Product Category	SRAM	SRAM	SRAM	SRAM	SRAM	SRAM
系列 Packaging	Reel	Tray	Tray	Reel	Tray	Reel
工厂包装数量 Factory Pack Quantity	800	72	72	800	72	800
Memory Size	18 Mbi	18 Mbi	18 Mbi	-	18 Mbi	18 Mbi
Access Time	7.5 ns	6.5 ns	7.5 ns	-	7.5 ns	7.5 ns
电源电压-最大 Supply Voltage - Max	3.3 V	2.625 V	3.3 V	-	3.465 V	3.465 V
Supply Voltage - Mi	2.5 V	2.375 V	2.5 V	-	3.135 V	3.135 V
Maximum Operating Curre	425 mA	450 mA	425 mA	-	475 mA	475 mA
最大工作温度 Maximum Operating Temperature	+ 70 C	+ 70 C	+ 70 C	-	+ 85 C	+ 85 C
最小工作温度 Minimum Operating Temperature	0 C	0 C	0 C	-	- 40 C	- 40 C
安装风格 Mounting Style	SMD/SMT	SMD/SMT	SMD/SMT	-	SMD/SMT	SMD/SMT
封装 / 箱体 Package / Case	TQFP-100	TQFP-100	TQFP-100	-	TQFP-100	TQFP-100
Maximum Clock Frequency	117 MHz	133 MHz	117 MHz	-	117 MHz	117 MHz
类型 Type	Synchronous Flow-Through SRAM	Synchronous	Synchronous Flow-Through SRAM	-	Synchronous	Synchronous

IS61NLF102418-7.5TQLI-TR

IS61NLF102418-7.5TQLI-TR概述

IS61NLF102418-7.5TQLI-TR规格参数

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IS61NLF102418-7.5TQLI-TR相似产品对比

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