FAN6921AML — Integrated Critical Mode PFC / Quasi-Resonant Current Mode PWM Controller
May 2013
FAN6921AML
Integrated Critical Mode PFC / Quasi-Resonant
Current Mode PWM Controller
Features
Integrated PFC and Flyback Controller
Critical Mode PFC Controller
Zero-Current Detection for PFC Stage
Quasi-Resonant Operation for PWM Stage
Internal Minimum t
off
8 µs for QR PWM Stage
Internal 10 ms Soft-Start for PWM
Brownout Protection
H/L Line Over-Power Compensation (OPC)
Latched Protection (FB Pin)
Over-Power / Overload Protection
Short-Circuit Protection
Open-Loop Protection
Description
The highly integrated FAN6921AML combines a Power
Factor Correction (PFC) controller and a Quasi-
Resonant PWM controller. Integration provides cost-
effect design and allows for fewer external components.
For PFC, FAN6921AML uses a controlled on-time
technique to provide a regulated DC output voltage and
to perform natural power factor correction. With an
innovative THD optimizer, FAN6921AML can reduce
input current distortion at zero-crossing duration to
improve THD performance.
For PWM, FAN6921AML enhances the power system
performance through valley detection, green-mode
operation, and high / low line over power compensation.
FAN6921AML provides: secondary-side open-loop and
over-current protection, external latch triggering,
adjustable over-temperature protection by RT pin and
external NTC resistor, internal over-temperature
shutdown, VDD pin OVP, and DET pin over-voltage for
output OVP, and brownin / out for AC input voltage
under-voltage protection (UVP).
The FAN6921AML controller is available in a 16-pin
small outline package (SOP).
Externally Latch Triggering (RT Pin)
Adjustable Over-Temperature Latched (RT Pin)
VDD Pin & Output Voltage OVP (Latched)
Internal Temperature Shutdown (140°C)
Applications
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Ordering Information
Part Number
FAN6921AMLMY
OLP Mode
Latch
Operating
Temperature Range
-40°C to +105°C
Package
16-Pin Small Outline Package (SOP)
Packing
Method
Tape & Reel
© 2011 Fairchild Semiconductor Corporation
FAN6921AML • Rev. 1.0.1
www.fairchildsemi.com
FAN6921AML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller
Application Diagram
14
6
4
3
1
16
ZCD
13
OPFC CSPFC INV RANGE HV
NC
15
VIN
FAN6921
GND
9
OPWM
RT
12
8
COMP
2
FB
11
DET VDD
10
7
CSPWM
5
Figure 1. Typical Application
© 2011 Fairchild Semiconductor Corporation
FAN6921AML • Rev. 1.0.1
www.fairchildsemi.com
2
FAN6921AML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller
Internal Block Diagram
COMP
HV
VDD
2
RANGE
2.65V
2.75V
Multi-Vector Amp.
2.75V
2.9V
2.3V
0.45V
RANGE
16
OVP
I
HV
27.5V
UVP
Debounce
70µs
OVP
7
Internal
Bias
Two Steps
UVLO
18V/10V/7.5V
DRV
15
NC
Latched
S
Latched
Brownout
SET
Q
15.5V
6
OPFC
INV
3
2.5V
THD
Optimizer
R
CLR
Q
Sawtooth
Generator
/t
ON-MAX-PFC
Disable
Function
0.2V
Debounce
550ms / 150µs
Timer
50ms
V
C
& PFC ON/OFF &
Multi Vector Amp.
ON/OFF
Restarter
PFC Zero Current
Detector
Inhibit
Timer
2.1V/1.75V
0.6V
PFC
Current Limit
CSPFC
4
Blanking
Circuit
V
CTL-PFC-ON/OFF
4.2V
2R
2.5ms
32.5µs
0.7V
I
ZCD
V
B
FB OLP
Starter
R
DRV
14
10V
ZCD
FB
11
Soft-Start
9.5ms
S
Blanking
Circuit
PWM
Current Limit
I
DET
SET
Q
17.5V
8
OPWM
CSPWM
5
R
CLR
Q
Over Power
Compensation
DET pin OVP
VDD pin OVP
Internal OTP
(RT Pin) Prog. OTP
Brownout
(RT Pin) Externally Triggering
Protection
Output Short Circuit (FB
Latched
Pin)
Output Open-Loop (FB Pin)
Output Over Power/ Overload (FB Pin)
V
C
Startup
V
B
& clamp
V
COMP
to 1.6V
Lathed
Protection
t
OFF-MIN
(8us/37µs/2.5ms)
I
DET
Valley
Detector
1
st
Valley
t
OFF-MIN
+9µs
Latched
t
OFF
Blanking
(4µs)
S/H
V
DET
Latched
2.5V
DET OVP
I
RT
1
RANGE
Debounce
Time
1.2V
0.8V V
INV
V
INV
1V/1.2V
100us
10ms
2.35V/2.15V
Brownout
comparator
DET
10
5V
I
DET
100uA
0.3V
0.8V
Debounce
100ms
Debounce
100ms
Internal
OTP
Latched
0.5V
Prog. OTP
/ Externally Triggering
9
GND
12
RT
13
VIN
PFC RANGE Control
Figure 2. Functional Block Diagram
© 2011 Fairchild Semiconductor Corporation
FAN6921AML • Rev. 1.0.1
www.fairchildsemi.com
3
FAN6921AML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller
Marking Information
16
ZXYTT
FAN6921AFO
TPM
1
- Fairchild Logo
Z
- Plant Code
X
- Year Code (1 Digit for SOP, 2-Digit for DIP)
Y
- Week Code (1 Digit for SOP, 2-Digit for DIP)
TT
–
Die-Run Code
F
- Frequency (M=LOW, H=HIGH Level)
O
- OLP Mode (L=Latch, R=Recovery)
T
- Package Type (N=DIP, M=SOP)
P
–
Y=Green Package
M
- Manufacture Flow Code
Figure 3. Marking Diagram
Pin Configuration
RANGE
COMP
INV
CSPFC
CSPWM
OPFC
VDD
OPWM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HV
N.C.
ZCD
VIN
RT
FB
DET
GND
Figure 4. Pin Configuration
Pin Definitions
Pin #
1
Name
RANGE
Description
RANGE pin’s impedance changes according to the VIN pin voltage level. When the input
voltage detected by the VIN pin is lower than a threshold voltage, it sets to high impedance;
whereas it sets to low impedance if input voltage is high level.
Output pin of the error amplifier. It is a transconductance type error amplifier for PFC output
voltage feedback. Proprietary multi-vector current is built-in to this amplifier; therefore, the
compensation for the PFC voltage feedback loop allows a simple compensation circuit between
this pin and GND.
Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage
divider and provides PFC output over- and under-voltage protections.
Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting
protection. When the sensed voltage across the PFC current-sensing resistor reaches the
internal threshold (0.6 typical), the PFC switch is turned off to activate cycle-by-cycle current
limiting.
Input to the comparator of the PWM over-current protection and performs PWM current-mode
control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch
and the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, current-
mode control, and high / low line over-power compensation according to DET pin source current
during PWM on time.
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage
is 15.5 V.
2
COMP
3
INV
4
CSPFC
5
CSPWM
6
OPFC
© 2011 Fairchild Semiconductor Corporation
FAN6921AML • Rev. 1.0.1
www.fairchildsemi.com
4
FAN6921AML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller
Pin Definitions
Pin #
7
8
9
Name
VDD
OPWM
GND
Description
Power supply. The threshold voltages for startup and turn-off are 18 V and 7.5 V, respectively.
The startup current is less than 30 µA and the operating current is lower than 10 mA.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The
clamped gate output voltage is 17.5 V.
The power ground and signal ground.
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider
for the following purposes:
Producing an offset voltage to compensate the threshold voltage of PWM current limit for
providing over-power compensation. The offset is generated in accordance with the input
voltage when PWM switch is on.
10
DET
Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on the PWM switch.
Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding.
This flat voltage is reflected to the secondary winding during PWM inductor discharge time. If
output OVP and this flat voltage is higher than 2.5 V, the controller enters latch mode and
stops all PFC and PWM switching operation.
Feedback voltage pin. This pin is used to receive the output voltage level signal to determine
PWM gate duty for regulating output voltage. The FB pin voltage can also activate open-loop,
overload, or output-short-circuit protection if the FB pin voltage is higher than a threshold of
around 4.2 V for more than 50 ms.The input impedance of this pin is a 5 kΩequivalent
resistance. A 1/3 attenuator is connected between the FB pin and the input of the CSPWM/FB
comparator.
Adjustable over-temperature protection and external latch triggering. A constant current flows
out of the RT pin. When RT pin voltage is lower than 0.8 V (typical), latch mode protection is
activated and stops all PFC and PWM switching operation until the AC plug is removed.
Line-voltage detection for brownin/out protections. This pin can receive the AC input voltage
level through a voltage divider. The voltage level of the VIN pin is not only used to control
RANGE pin’s status, but it can also perform brownin/out protection for AC input voltage UVP.
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled
to PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current
discharges to zero. When the ZCD voltage signal is detected, the controller starts a new PFC
switching cycle. When the ZCD pin voltage is pulled to under 0.2 V (typical), it disables the PFC
stage and the controller stops PFC switching. This can be realized with an external circuit if
disabling the PFC stage is desired.
No connection
High-voltage startup. HV pin is connected to the AC line voltage through a resistor (100 kΩ
typical) for providing a high-charging current to V
DD
capacitor.
11
FB
12
RT
13
VIN
14
ZCD
15
16
NC
HV
© 2011 Fairchild Semiconductor Corporation
FAN6921AML • Rev. 1.0.1
www.fairchildsemi.com
5
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