ispClock 5500 Family
™
In-System Programmable Clock Generator
with Universal Fan-Out Buffer
February 2005
Data Sheet
Features
■
■
■
■
10MHz to 320MHz Input/Output Operation
Low Output to Output Skew (<50ps)
Low Jitter Peak-to-Peak(<70ps)
Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,
LVPECL
• Programmable precision output impedance
- 40 to 70
Ω
in 5
Ω
increments
• Programmable slew rate
• Up to 10 banks with individual V
CCO
and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■
Up to Five Clock Frequency Domains
■
Flexible Clock Reference Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL
• Clock A/B selection multiplexer
• Programmable precision termination
■
Four User-programmable Profiles Stored in
E
2
CMOS
®
Memory
• Supports both test and multiple operating
configurations
■
Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (5 bits)
- Internal feedback divider (5 bits)
- Five output dividers (5 bits)
• Programmable On-chip Loop Filter
■
Full JTAG Boundary Scan Test In-System
Programming Support
■
Exceptional Power Supply Noise Immunity
■
Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■
100-pin and 48-pin TQFP Packages
■
Applications
• Circuit board common clock generation and
distribution
• PLL-based frequency generation
• High fan-out clock buffer
■
Precision Programmable Phase Adjustment
(Skew) Per Output
• 16 settings; minimum step size 195ps
- Locked to VCO frequency
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
Product Family Block Diagram
LOCK DETECT
OUTPUT
DIVIDERS
BYPASS
MUX
*
M
FILTER
VCO
V3
V4
PLL CORE
OUTPUT
ROUTING
MATRIX
CLOCK OUTPUTS
PHASE/
FREQUENCY
DETECTOR
N
V2
V0
V1
SKEW
CONTROL
OUTPUT
DRIVERS
REFERENCE
INPUTS
JTAG
INTERFACE
&
E
2
CMOS
MEMORY
Multiple Profile
Management Logic
0
1
2
3
INTERNAL FEEDBACK PATH
* Input Available only on ispClock 5520
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
clk5500_06.1
Lattice Semiconductor
ispClock5500 Family Data Sheet
General Description and Overview
The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed
for use in high performance communications and computing applications. The ispClock5510 provides up to 10 sin-
gle-ended or five differential clock outputs, while the ispClock5520 provides up to 20 single-ended or 10 differential
clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS,
LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro-
grammable control of termination, slew-rate, and timing skew. All configuration information is stored on-chip in non-
volatile E
2
CMOS memory.
The ispClock5500’s PLL and divider systems supports the synthesis of clock frequencies differing from that of the
reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-divid-
ers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback
may be taken from the output of any of the five V-dividers.
The core functions of all members of the ispClock5500 family are identical, the differences between devices being
restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional
block diagrams of the ispClock5510 and ispClock5520.
Table 1. ispClock5500 Family Members
Device
ispClock5510
ispClock5520
Ref. Input Pairs
1
2
Clock Outputs
10
20
Figure 1. ispClock5510 Functional Block Diagram
PS0
PS1
LOCK
RESET
PLL_BYPASS
SGATE
GOE
OEX
OEY
Profile Select
Control
OUTPUT ENABLE CONTROLS
0
1
2
3
LOCK
DETECT
OUTPUT
DIVIDERS
V0
(2-64)
OUTPUT ROUTING
MATRIX
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
BANK_4A
BANK_4B
INPUT
DIVIDER
REFA+
REFA-
REFVTT
M
(1-32)
V1
(2-64)
1
PHASE
DETECT
LOOP
FILTER
V2
(2-64)
VCO
0
V3
(2-64)
N
(1-32)
FEEDBACK
DIVIDER
FEEDBACK
SKEW ADJUST
V4
(2-64)
JTAG INTERFACE
TDI
TMS
TCK
TDO
2
Lattice Semiconductor
Figure 2. ispClock5520 Functional Block Diagram
PS0
PS1
LOCK
RESET
PLL_BYPASS
SGATE
GOE
OEX
ispClock5500 Family Data Sheet
OEY
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_0A
BANK_0B
BANK_1A
Profile Select
Control
OUTPUT ROUTING
MATRIX
OUTPUT ENABLE CONTROLS
0
1
2
3
LOCK
DETECT
BANK_1B
BANK_2A
BANK_2B
OUTPUT
DIVIDERS
V0
BANK_3A
BANK_3B
BANK_4A
REFSEL
REFA+
REFA-
0
(2-64)
INPUT
DIVIDER
M
(1-32)
1
V1
(2-64)
BANK_4B
REFVTT
1
REFB+
REFB-
PHASE
DETECT
LOOP
FILTER
V2
(2-64)
VCO
0
V3
(2-64)
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_5A
BANK_5B
N
(1-32)
FEEDBACK
DIVIDER
V4
(2-64)
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
JTAG INTERFACE
FEEDBACK
SKEW ADJUST
BANK_9B
TDI
TMS
TCK
TDO
3
Lattice Semiconductor
ispClock5500 Family Data Sheet
Absolute Maximum Ratings
ispClock5500V
Core Supply Voltage V
CCD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
PLL Supply Voltage V
CCA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
JTAG Supply Voltage V
CCJ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Output Driver Supply Voltage V
CCO
. . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Output Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130°C
1. When applied to an output when in high-Z condition
Recommended Operating Conditions
ispClock5500V
Symbol
V
CCD
V
CCJ
V
CCA
V
CCASLEW
T
JOP
T
A
Parameter
Core Supply Voltage
JTAG I/O Supply Voltage
Analog Supply Voltage
V
CCA
Turn-on Ramp Rate
Operating Junction Temperature
Ambient Operating Temperature
Commercial
Industrial
Commercial
Industrial
Conditions
Min.
3.0
1.62
3.0
—
0
-40
0
-40
Max.
3.6
3.6
3.6
0.033
100
115
70
1
85
1
Units
V
V
V
V/µs
°C
°C
1. Device power dissipation may also limit maximum ambient operating temperature.
Recommended Operating Conditions – V
CCO
vs. Logic Standard
V
CCO
(V)
Logic Standard
LVTTL
LVCMOS 1.8V
LVCMOS 2.5V
LVCMOS 3.3V
SSTL2 Class 1
SSTL3 Class 1
HSTL Class 1
LVPECL (Differential)
LVDS
V
CCO
= 2.5V
V
CCO
= 3.3V
Min.
3.0
1.71
2.375
3.0
2.375
3.0
1.425
3.0V
2.375
3.0
Typ.
3.3
1.8
2.5
3.3
2.5
3.3
1.5
3.3V
2.5V
3.3
Max.
3.6
1.89
2.625
3.6
2.625
3.6
1.575
3.6V
2.625
3.6
Min.
—
—
—
—
1.15
1.30
0.68
—
—
—
V
REF
(V)
Typ.
—
—
—
—
1.25
1.50
0.75
—
—
—
Max.
—
—
—
—
1.35
1.70
0.90
—
—
—
Min.
—
—
—
—
V
REF
- 0.04
V
REF
- 0.05
—
—
—
—
V
TT
(V)
Typ.
—
—
—
—
—
V
REF
0.5 x V
CCO
—
—
—
Max.
—
—
—
—
V
REF
+ 0.04
V
REF
+ 0.05
—
—
—
—
Note: ‘—’ denotes V
REF
or V
TT
not applicable to this logic standard
E
2
CMOS Memory Write/Erase Characteristics
Parameter
Erase/Reprogram Cycles
Conditions
Min.
1000
Typ.
—
Max.
—
Units
4
Lattice Semiconductor
ispClock5500 Family Data Sheet
Performance Characteristics – Power Supply
Symbol
I
CCD
I
CCA
I
CCO
Parameter
Core Supply Current
Analog Supply Current
Output Driver Supply Current
(per Bank)
Conditions
ispClock5510, f
VCO
= 640MHz
ispClock5520, f
VCO
= 640MHz
f
VCO
= 640MHz
V
CCO
= 1.8V
1
, LVCMOS
V
CCO
= 2.5V
1
, LVCMOS
V
CCO
= 3.3V
1
, LVCMOS
V
CCO
= 3.3V
2
, LVDS
V
CCJ
= 1.8V
V
CCJ
= 2.5V
V
CCJ
= 3.3V
Typ.
100
130
5.5
13
18
24
7.5
200
300
300
Max.
110
150
7
15
24
35
8
300
400
400
Units
mA
mA
mA
mA
I
CCJ
JTAG I/O Supply Current (static)
µA
1. Supply current consumed by each bank, both outputs active, 18pF load, 320MHz output frequency.
2. Supply current consumed by each bank, 100
Ω
/5pF differential load, 320MHz output frequency.
DC Electrical Characteristics – Single-ended Logic
V
IL
(V)
Logic Standard
LVTTL/LVCMOS 3.3V
LVCMOS 1.8V
LVCMOS 2.5V
SSTL2 Class 1
SSTL3 Class 1
HSTL Class 1
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max.
0.8
0.68
0.7
V
REF
- 0.2
V
REF
- 0.1
Min.
2
1.07
1.7
V
REF
+ 0.2
V
REF
+ 0.1
V
IH
(V)
Max.
3.6
3.6
3.6
3.6
3.6
3.6
V
OL
Max. (V) V
OH
Min. (V)
0.4
0.4
0.4
0.54
2
0.9
2
I
OL
(mA)
4
1
4
1
4
1
7.6
8
8
I
OH
(mA)
-4
1
-4
1
-4
1
-7.6
-8
-8
V
CCO
- 0.4
V
CCO
- 0.4
V
CCO
- 0.4
V
CCO
- 0.81
2
V
CCO
- 1.3
2
V
REF
- 0.18 V
REF
+ 0.18
0.4
3
V
CCO
- 0.4
3
1. Specified for 50Ω internal series output termination.
2. Specified for 40Ω internal series output termination.
3. Specified for
≈20Ω
internal series output termination.
DC Electrical Characteristics – LVDS
Symbol
V
ICM
V
THD
V
IN
V
OH
V
OL
V
OD
∆V
OD
V
OS
∆V
OS
I
SA
I
SAB
Parameter
Common Mode Input Voltage
Differential Input Threshold
Input Voltage
Output High Voltage
Output Low Voltage
Output Voltage Differential
Change in V
OD
between H and L
Output Voltage Offset
Change in V
OS
Between H and L
Output Short Circuit Current
Output Short Circuit Current
V
OD
= 0V, Outputs Shorted to GND
V
OD
= 0V, Outputs Shorted to Each Other
Common Mode Output Voltage
R
T
= 100Ω
R
T
= 100Ω
R
T
= 100Ω
Conditions
V
THD
≤
100mV
V
THD
≤
150mV
Min.
V
THD
/2
V
THD
/2
±100
0
—
0.9
250
—
1.125
—
—
—
—
—
1.375
1.03
400
—
1.20
—
—
—
Typ.
—
Max.
2.0
2.325
—
2.4
1.60
—
480
50
1.375
50
24
12
Units
V
V
mV
V
V
V
mV
mV
V
mV
mA
mA
5
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