IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
14-BIT REGISTERED
BUFFER WITH SSTL I/O
IDT74SSTV16857
FEATURES:
• 1:1 registered buffer
• Meets or exceeds JEDEC standards for SSTV16857 and
SSTVN16857
• 2.3V to 2.7V operation for PC1600, PC2100, and PC2700
• 2.5V to 2.7V operation for PC3200
• SSTL_2 Class II style data inputs/outputs
• Differential CLK input
•
RESET
control compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Drive up to equivalent of 18 SDRAM loads
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in TSSOP package
DESCRIPTION:
The SSTV16857 is a 14-bit registered buffer designed for 2.3V-2.7V
V
DD
for PC1600-PC2700, and 2.5V-2.7V V
DD
for PC3200, and supports
low standby operation. All data inputs and outputs are SSTL_2 level
compatible with JEDEC standard for SSTL_2.
RESET
is an LVCMOS input since it must operate predictably during the
power-up phase.
RESET,
which can be operated independent of CLK and
CLK,
must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET,
when in the low state, will disable all input receivers, reset all
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of
RESET.
APPLICATIONS:
• Along with CSPT857C/D, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs
FUNCTIONAL BLOCK DIAGRAM
RESET
34
CK
CK
38
39
V
REF
D1
35
48
1D
C1
R
1
Q1
TO 13 OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
c
2003 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
February 2009
DSC-5737/8
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
Q
1
Q
2
GND
V
DDQ
Q
3
Q
4
Q
5
GND
V
DDQ
Q
6
Q
7
V
DDQ
GND
Q
8
Q
9
V
DDQ
GND
Q
10
Q
11
Q
12
V
DDQ
GND
Q
13
Q
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D
1
D
2
GND
V
DD
D
3
D
4
D
5
D
6
D
7
CLK
CLK
V
DD
GND
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
I
(2)
V
O
(3)
I
IK
I
OK
I
O
V
DD
T
STG
Description
Input Voltage Range
Output Voltage Range
Input Clamp Current, V
I
< 0
Output Clamp Current,
V
O
< 0 or V
O
> V
DDQ
Continuous Output Current,
V
O
= 0 to V
DDQ
Continuous Current through each
V
DD
, V
DDQ
or GND
Storage Temperature Range
–65 to +150
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. The output current will flow if the following conditions are observed:
a) Output in HIGH state
b) V
O
= V
DDQ
Max.
–0.5 to 3.6
–0.5 to V
DD
+0.5
–0.5 to V
DDQ
+0.5
–50
±50
±50
±100
Unit
V
V
V
mA
mA
mA
mA
V
DD
or V
DDQ
Supply Voltage Range
V
REF
RESET
D
8
D
9
D
10
D
11
D
12
V
DD
GND
D
13
D
14
FUNCTION TABLE
(1)
Input
RESET
H
H
H
L
CLK
↑
↑
L or H
X
CLK
↓
↓
L or H
X
D
L
H
X
X
Q Outputs
L
H
Q
(2)
L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW to HIGH
↓
= HIGH to LOW
2. Q = Output level before the indicated steady-state conditions were established.
TSSOP
TOP VIEW
2
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (PC1600-PC2700)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C, V
DD
= 2.5V ±0.2V, V
DDQ
= 2.5V ±0.2V
Symbol
V
IK
V
OH
V
OL
I
I
I
DD
I
DDD
All Inputs
Static Standby
Static Operating
Dynamic Operating (Clock Only)
Dynamic Operating
(Per Each Data Input)
r
OH
r
OL
r
O(Δ)
C
I
Output HIGH
Output LOW
| r
OH
- r
OL
| each separate bit
Data Inputs
CLK and
CLK
RESET
Parameter
Control Inputs
Test Conditions
V
DD
= 2.3V, I
I
=
−18mA
V
DD
= 2.3V to 2.7V, I
OH
= -100μA
V
DD
= 2.3V, I
OH
= -16mA
V
DD
= 2.3V to 2.7V, I
OL
= 100μA
V
DD
= 2.3V, I
OL
= 16mA
V
DD
= 2.7V, VI = V
DD
or GND
I
O
= 0, V
DD
= 2.7V,
RESET
= GND
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
,
CLK and
CLK
Switching 50% Duty Cycle.
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
,
CLK and
CLK
Switching 50% Duty Cycle. One Data Input
Switching at Half Clock Frequency, 50% Duty Cycle.
V
DD
= 2.3V to 2.7V, I
OH
= -20mA
V
DD
= 2.3V to 2.7V, I
OH
= 20mA
V
DD
= 2.5V, T
A
= 25°C, I
OH
= -20mA
V
DD
= 2.5V, V
I
= V
REF
±
310mV
V
ICR
= 1.25V, V
I (PP)
= 360mV
V
I
= V
DD
or GND
7
7
—
2.5
2.5
—
—
—
—
—
—
—
20
20
4
3.5
3.5
—
pF
—
—
—
Min.
—
V
DD
– 0.2
1.95
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
Max.
–1.2
—
—
0.2
0.35
±5
0.01
—
—
μA/Clock
MHz
μA/Clock
MHz/Data
Input
Ω
Ω
Ω
μA
mA
V
Unit
V
V
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (PC3200)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C, V
DD
= 2.6V ±0.1V, V
DDQ
= 2.6V ±0.1V
Symbol
V
IK
V
OH
V
OL
I
I
I
DD
I
DDD
All Inputs
Static Standby
Static Operating
Dynamic Operating (Clock Only)
Dynamic Operating
(Per Each Data Input)
r
OH
r
OL
r
O(Δ)
C
I
Output HIGH
Output LOW
| r
OH
- r
OL
| each separate bit
Data Inputs
CLK and
CLK
RESET
Parameter
Control Inputs
Test Conditions
V
DD
= 2.5V, I
I
=
−18mA
V
DD
= 2.5V to 2.7V, I
OH
= -100μA
V
DD
= 2.5V, I
OH
= -16mA
V
DD
= 2.5V to 2.7V, I
OL
= 100μA
V
DD
= 2.5V, I
OL
= 16mA
V
DD
= 2.7V, VI = V
DD
or GND
I
O
= 0, V
DD
= 2.7V,
RESET
= GND
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
,
CLK and
CLK
Switching 50% Duty Cycle.
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
,
CLK and
CLK
Switching 50% Duty Cycle. One Data Input
Switching at Half Clock Frequency, 50% Duty Cycle.
V
DD
= 2.5V to 2.7V, I
OH
= -20mA
V
DD
= 2.5V to 2.7V, I
OH
= 20mA
V
DD
= 2.6V, T
A
= 25°C, I
OH
= -20mA
V
DD
= 2.6V, V
I
= V
REF
±
310mV
V
ICR
= 1.3V, V
I (PP)
= 360mV
V
I
= V
DD
or GND
7
7
—
2.5
2.5
—
—
—
—
—
—
—
20
20
4
3.5
3.5
—
pF
—
—
—
Min.
—
V
DD
– 0.2
1.95
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
Max.
–1.2
—
—
0.2
0.35
±5
0.01
—
—
μA/Clock
MHz
μA/Clock
MHz/Data
Input
Ω
Ω
Ω
μA
mA
V
Unit
V
V
3
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS (PC1600-PC2700), T
A
= 25ºC
(1)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
I
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
ICR
V
I (PP)
I
OH
I
OL
T
A
NOTE:
1.
The
RESET
input of the device must be held at V
DD
or GND to ensure proper device operation.
Parameter
Supply Voltage
Output Supply Voltage
Reference Voltage (V
REF
= V
DDQ
/2)
Termination Voltage
Input Voltage
AC High-Level Input Voltage
AC Low-Level Input Voltage
DC High-Level Input Voltage
DC Low-Level Input Voltage
High-Level Input Voltage
Low-Level Input Voltage
Common-Mode Input Range
Peak-to-Peak Input Voltage
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
Data Inputs
Data Inputs
Data Inputs
Data Inputs
RESET
RESET
CLK,
CLK
CLK,
CLK
Min.
V
DDQ
2.3
1.15
V
REF
– 40mV
0
V
REF
+ 310mV
—
V
REF
+ 150mV
—
1.7
—
0.97
360
—
—
– 40
Typ.
—
2.5
1.25
V
REF
—
—
—
—
—
—
—
—
—
—
—
—
Max.
2.7
2.7
1.35
V
REF
+ 40mV
V
DD
—
V
REF
– 310mV
—
V
REF
– 150mV
—
0.7
1.53
—
– 20
20
+85
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mV
mA
°C
OPERATING CHARACTERISTICS (PC3200), T
A
= 25ºC
(1)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
I
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
ICR
V
I (PP)
I
OH
I
OL
T
A
NOTE:
1.
The
RESET
input of the device must be held at V
DD
or GND to ensure proper device operation.
Parameter
Supply Voltage
Output Supply Voltage
Reference Voltage (V
REF
= V
DDQ
/2)
Termination Voltage
Input Voltage
AC High-Level Input Voltage
AC Low-Level Input Voltage
DC High-Level Input Voltage
DC Low-Level Input Voltage
High-Level Input Voltage
Low-Level Input Voltage
Common-Mode Input Range
Peak-to-Peak Input Voltage
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
Data Inputs
Data Inputs
Data Inputs
Data Inputs
RESET
RESET
CLK,
CLK
CLK,
CLK
Min.
V
DDQ
2.5
1.25
V
REF
– 40mV
0
V
REF
+ 310mV
—
V
REF
+ 150mV
—
1.7
—
0.97
360
—
—
– 40
Typ.
—
2.5
1.3
V
REF
—
—
—
—
—
—
—
—
—
—
—
—
Max.
2.7
2.7
1.35
V
REF
+ 40mV
V
DD
—
V
REF
– 310mV
—
V
REF
– 150mV
—
0.7
1.53
—
– 20
20
+85
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mV
mA
°C
4
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
PC1600 - PC2700
Symbol
CLOCK
PC3200
Min.
—
2.5
—
—
0.65
0.75
0.75
0.9
Max.
220
—
22
22
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Parameter
Clock Frequency
Pulse Duration, CLK,
CLK
HIGH or LOW
Differential Inputs Active Time
(1)
Differential Inputs Inactive Time
(2)
Setup Time, Fast Slew Rate
(3, 5)
Min.
—
2.5
—
—
Data Before CLK↑, CLK↓
Data Before CLK↑, CLK
↓
0.65
0.75
0.75
0.9
Max.
200
—
22
22
—
—
—
—
tw
t
ACT
t
INACT
t
SU
t
H
Setup Time, Slow Slew Rate
(4, 5)
Hold Time, Fast Slew Rate
(3,5)
Hold Time, Slow Slew Rate
(2,5)
NOTES:
1. Data inputs must be low a minimum time of t
ACT
max., after
RESET
is taken HIGH.
2. Data and clock inputs must be held at valid levels (not floating) a minimum time of t
INACT
max., after
RESET
is taken LOW.
3. For data signal input slew rate is
≥1V/ns.
4. For data signal input slew rate is
≥0.5V/ns
and <1V/ns.
5. CLK,
CLK
signal input slew rates are
≥1V/ns.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
PC1600 - PC2700
Symbol
f
MAX
t
PDM
t
PDMSS
t
PHL
Parameter
CLK and
CLK
to Q
CLK and
CLK
to Q (simultaneous switching)
RESET
to Q
Min.
200
1.1
—
—
Max.
—
2.8
—
5
Min.
220
1.1
—
—
PC3200
Max.
—
2.4
(1)
2.7
5
Unit
MHz
ns
ns
ns
NOTE:
1. 2.8ns for parts assembled and tested prior to WW14, 2004.
5
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