FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
NRND – Not Recommend for New Designs - 8/30/2013
For Replacement Device Use ICS840N011BGI
ICS840011
NRND
G
ENERAL
D
ESCRIPTION
The ICS840011 is a Fibre Channel Clock Generator and a
member of the HiPerClocks
TM
family of high performance
devices from IDT. The ICS840011 uses a 26.5625MHz or 25MHz
crystal to syn-thesize 106.25MHz or 100MHz respectively. The
ICS840011 has excellent phase jitter performance, from 637kHz
– 10MHz integration range. The ICS840011 is packaged in a
small 8-pin TSSOP, making it ideal for use in systems with limited
board space.
F
EATURES
•
One LVCMOS/LVTTL output, 7Ω output impedence
•
Crystal oscillator interface designed for 26.5625MHz or
25MHz, 18pF parallel resonant crystal
•
Output frequency: 106.25MHz (typical)
•
VCO range: 560MHz to 680MHz
•
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.780ps (typical)
•
RMS phase noise at 125MHz:
Offset
Noise Power
100Hz ............... -95.7 dBc/Hz
1kHz ................ -121 dBc/Hz
10kHz ................ -129 dBc/Hz
100kHz ............. -129.6 dBc/Hz
•
3.3V operating supply
•
-30°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
•
Not Recommended for New Designs
•
For New Designs Use ICS840N011BGI
F
REQUENCY
T
ABLE
Inputs
Crystal Frequency (MHz)
26.5625
25
Output Frequency
(MHz)
106.25
100
B
LOCK
D
IAGRAM
OE (Pullup)
XTAL_IN
P
IN
A
SSIGNMENT
VCO
637.5MHz w/
26.5625MHz Ref.
OSC
XTAL_OUT
Phase
Detector
÷6
Q0
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q0
GND
nc
ICS840011
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
M = ÷24 (fixed)
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
1
ICS840011AG REV. A AUGUST 30, 2013
ICS840011
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3,
4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
nc
GND
Q0
V
DD
Power
Input
Input
Unused
Power
Output
Power
Pullup
Type
Description
Analog supply pin.
Output enable pin. When HIGH, Q0 output is enabled.
When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
No connect.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
7Ω output impedance.
Core supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Output Impedance
5
V
DD
, V
DDA
= 3.465V
Test Conditions
Minimum
Typical
4
24
51
7
12
Maximum
Units
pF
pF
kΩ
Ω
T
ABLE
3. C
ONTROL
F
UNCTION
T
ABLE
Control Inputs
OE
0
1
Output
Q0
Hi-Z
Active
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
2
ICS840011AG REV. A AUGUST 30, 2013
ICS840011
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
101.7°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -30°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
80
10
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -30°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
V
V
Output High Voltage; NOTE 1
V
OL
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DD
/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
26.5625
50
7
MHz
Ω
pF
Maximum
Units
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -30°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
fOUT = 106.25MHz,
(637kHz to 10MHz)
20% to 80%
fOUT = 106.25MHz
Minimum
93.33
Typical
106.25
0.780
250
48
600
52
Maximum
113.33
Units
MHz
ps
ps
%
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
All parameters are characterized @ 106.25MHz.
NOTE 1: Please refer to the Phase Noise Plot.
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
3
ICS840011AG REV. A AUGUST 30, 2013
ICS840011
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
T
YPICAL
P
HASE
N
OISE AT
106.25MH
Z
-10
-20
-30
-40
-50
-60
➤
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637K to 10MHz = 0.780ps
0
N
OISE
P
OWER
dBc
Hz
-70
-80
-90
-100
-110
Raw Phase Noise Data
➤
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
➤
10k
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
4
ICS840011AG REV. A AUGUST 30, 2013
ICS840011
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V ± 5%
Phase Noise Plot
Noise Power
V
DD
Qx
SCOPE
Phase Noise Mask
LVCMOS
GND
f
1
Offset Frequency
f
2
-1.65V ± 5%
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V LVCMOS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
RMS P
HASE
J
ITTER
80%
Q0
80%
20%
t
PW
t
PERIOD
Clock
Outputs
20%
t
R
t
F
odc =
t
PW
t
PERIOD
x 100%
LVCMOS O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
LVCMOS O
UTPUT
R
ISE
/F
ALL
T
IME
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
5
ICS840011AG REV. A AUGUST 30, 2013
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
