EVALUATION KIT AVAILABLE
MAX11129–MAX11132
3Msps, Low-Power, Serial 12-/10-Bit,
8-/16-Channel ADCs
General Description
The MAX11129–MAX11132 are 12-/10-bit with external
reference and industry-leading 1.5MHz, full linear band-
width, high speed, low-power, serial output successive
approximation register (SAR) analog-to-digital convert-
ers (ADCs). The MAX11129–MAX11132 include both
internal and external clock modes.
These devices feature
scan mode in both internal and external clock modes.
The internal clock mode features internal averaging
to
increase SNR.
The external clock mode features the
SampleSetK technology, a user-programmable analog
input channel sequencer.
The
SampleSet
approach
provides greater sequencing flexibility for multichannel
applications while alleviating significant microcontroller
or DSP (controlling unit) communication overhead.
The internal clock mode features an integrated FIFO
allowing data to be sampled at high speeds and then held
for readout at any time or at a lower clock rate. Internal
averaging is also supported in this mode improving SNR
for noisy input signals. The devices feature analog input
channels that can be configured to be single-ended
inputs, fully differential pairs, or pseudo-differential inputs
with respect to one common input.
The
MAX11129–
MAX11132
operate from a 2.35V to 3.6V supply and con-
sume only 15.2mW at 3Msps.
The MAX11129–MAX11132 include
AutoShutdownK,
fast wake-up, and a high-speed 3-wire serial interface.
The devices feature full power-down mode for optimal
power management.
The
48MHz,
3-wire serial interface directly connects to
SPI, QSPIK, and MICROWIRE
M
devices without external
logic.
Excellent dynamic performance, low voltage, low power,
ease of use, and small package size make these convert-
ers ideal for portable battery-powered data-acquisition
applications, and for other applications that demand low
power consumption and small space.
The MAX11129–MAX11132 are available in 28-pin, 5mm
x 5mm, TQFN packages and the MAX11131 is available
in a 28-pin TSSOP package. All devices operate over the
-40NC to +125NC temperature range.
SampleSet and AutoShutdown are trademarks of Maxim
Integrated Products, Inc.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
Benefits and Features
S
Scan Modes, Internal Averaging, and Internal
Clock
S
16-Entry First-In/First-Out (FIFO)
S
SampleSet: User-Defined Channel Sequence with
Maximum Length of 256
S
Analog Multiplexer with True Differential
Track/Hold
16-/8-Channel Single-Ended
8-/4-Channel Fully-Differential Pairs
15-/8-Channel Pseudo-Differential Relative to
a Common Input
S
Two Software-Selectable Bipolar Input Ranges
QV
REF+
/2,
QV
REF+
S
Flexible Input Configuration Across All Channels
S
High Accuracy
Q1
LSB INL,
Q1
LSB DNL, No Missing Codes
Over Temperature Range
S
70dB SINAD Guaranteed at 500kHz Input
Frequency
S
1.5V to 3.6V Wide Range I/O Supply
Allows the Serial Interface to Connect Directly
to 1.8V, 2.5V, or 3.3V Digital Systems
S
2.35V to 3.6V Supply Voltage
S
Longer Battery Life for Portable Applications
Low Power
15.2mW at 3Msps with 3V Supplies
2µA Full-Shutdown Current
S
External Differential Reference (1V to V
DD
)
S
48MHz, 3-Wire SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial Interface
S
Wide -40NC to +125NC Operation
S
Space-Saving, 28-Pin, 5mm x 5mm TQFN
Packages
S
3Msps Conversion Rate, No Pipeline Delay
S
12-/10-Bit Resolution
Applications
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
Industrial Control Systems
Medical Instrumentation
Battery-Powered Instruments
Portable Systems
Ordering Information
appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to
www.maximintegrated.com/MAX11129.related.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6026; Rev 5; 9/12
MAX11129–MAX11132
3Msps, Low-Power, Serial 12-/10-Bit,
8-/16-Channel ADCs
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND.............................................................-0.3V to +4V
OVDD, AIN0–AIN13,
CNVST/AIN14,
REF+, REF-/AIN15
to GND......................-0.3V to the lower of (V
DD
+ 0.3V) and +4V
CS,
SCLK, DIN, DOUT,
EOC
TO GND ..... -0.3V to the Lower of
(V
OVDD
+ 0.3V) and +4V
DGND to GND ......................................................-0.3V to +0.3V
Input/Output Current (all pins) ...........................................50mA
Continuous Power Dissipation (T
A
= +70NC)
TQFN (derate 34.4mW/NC above +70NC)..................2758mW
TSSOP (derate 27mW/NC above +70NC)...................2162mW
Operating Temperature Range ........................ -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (B
JA
)
...........29NC/W
Junction-to-Case Thermal Resistance (B
JC
)..................2NC/W
TSSOP
Junction-to-Ambient Thermal Resistance (B
JA
)
...........37NC/W
Junction-to-Case Thermal Resistance (B
JC
)..................2NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS (MAX11131/MAX11132)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 3Msps, f
SCLK
= 48MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Offset Error Temperature
Coefficient
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
Line Rejection
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
(Up to the 5th Harmonic)
Spurious-Free Dynamic Range
Intermodulation Distortion
PSR
SINAD
SNR
THD
SFDR
IMD
f
1
= 398.4375kHz, f
2
= 275.8125kHz
79
(Note 6)
70
70
DYNAMIC PERFORMANCE (500kHz, input sine wave) (Notes 3 and 7)
72.2
72.3
-88
90
-85
-78
dB
dB
dB
dB
dB
OE
TC
GE
TC
(Note 5)
RES
INL
DNL
No missing codes
-0.1
+0.3
±2
±0.8
±0.5
±0.5
±2
12 bit
12
±1.0
±1.0
±4.0
±4.0
Bits
LSB
LSB
LSB
LSB
ppm/NC
ppm/NC
LSB
LSB/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maxim Integrated
2
MAX11129–MAX11132
3Msps, Low-Power, Serial 12-/10-Bit,
8-/16-Channel ADCs
ELECTRICAL CHARACTERISTICS (MAX11131/MAX11132) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 3Msps, f
SCLK
= 48MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
Full-Power Bandwidth
Full-Linear Bandwidth
SYMBOL
-3dB
-0.1dB
SINAD > 70dB
-0.5dB below full scale of
492.1875kHz sine wave input to the
channel being sampled, apply full-
scale 398.4375kHz sine wave signal
to all 15 nonselected input channels
t
PU
t
ACQ
Internally clocked (Note 8)
Conversion Time
External Clock Frequency
Aperture Delay
Aperture Jitter
ANALOG INPUT
Unipolar (single-ended and pseudo
differential)
Input Voltage Range
V
INA
Bipolar
(Note 9)
RANGE bit set to 0
RANGE bit set to 1
0
-V
REF+
/2
-V
REF+
-0.1
-0.1
15
pF
7.5
V
REF+
V
REF+
/2
V
REF+
V
REF+
+ 0.1
±1.5
V
FA
V
RMS
t
CONV
f
SCLK
Externally clocked, f
SCLK
= 48MHz,
16 cycles (Note 8)
333
0.48
8
30
48
Conversion cycle, external clock
52
2.1
CONDITIONS
MIN
TYP
50
7.5
1.5
MAX
UNITS
MHz
MHz
Crosstalk
-88
dB
CONVERSION RATE
Power-Up Time
Acquisition Time
2
Cycles
ns
µs
ns
MHz
ns
ps
Absolute Input Voltage Range
Static Input Leakage Current
I
ILA
C
AIN
AIN+, AIN- relative to GND
V
AIN_
= V
DD
, GND
During acquisition time,
RANGE bit = 0 (Note 10)
During acquisition time,
RANGE bit = 1 (Note 10)
Input Capacitance
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
REF+ Input Voltage Range
REF+ Input Current
V
REF-
V
REF+
I
REF+
V
REF+
= 2.5V, f
SAMPLE
= 3Msps
V
REF+
= 2.5V, f
SAMPLE
= 0
-0.3
1
110
0.1
+1
V
DD
+ 50mV
V
V
FA
Maxim Integrated
3
MAX11129–MAX11132
3Msps, Low-Power, Serial 12-/10-Bit,
8-/16-Channel ADCs
ELECTRICAL CHARACTERISTICS (MAX11131/MAX11132) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 3Msps, f
SCLK
= 48MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
SCLK Clock Period
SCLK Duty Cycle
SCLK Fall to DOUT Transition
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS
Fall to SCLK Fall Setup
SCLK Fall to
CS
Fall Hold
CNVST
Pulse Width
CS
or
CNVST
Rise to
EOC
Low
(Note 6)
CS
Pulse Width
t
DOE
t
DS
t
DH
t
CSS
t
CSH
t
CSW
t
CNV_INT
t
CSBW
See Figure 6
See Figure 7, f
SAMPLE
= 3Msps
5
SYMBOL
t
CP
t
CH
t
DOT
t
DOD
C
LOAD
=
10pF
V
OVDD
= 1.5V to 2.35V
V
OVDD
= 2.35V to 3.6V
CONDITIONS
Externally clocked conversion
MIN
20.8
40
4
4
60
16.5
15
15
16
14
4
1
4
1
5
1.7
2.4
TYP
MAX
UNITS
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fs
ns
TIMING CHARACTERISTICS (Figure 1) (Note 11)
C
LOAD
= 10pF, channel ID on
C
LOAD
= 10pF, channel ID off
C
LOAD
= 10pF
ELECTRICAL CHARACTERISTICS (MAX11129/MAX11130)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 3Msps, f
SCLK
= 48MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Offset Error Temperature
Coefficient
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
Line Rejection
PSR
(Note 6)
OE
TC
GE
TC
(Note 5)
RES
INL
DNL
No missing codes
0.3
0.1
±2
±0.8
±0.5
0.2
±1.0
10 bit
10
±0.4
±0.4
±1.0
±1.2
Bits
LSB
LSB
LSB
LSB
ppm/NC
ppm/NC
LSB
LSB/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maxim Integrated
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
