P4C1024
HIGH SPEED 128K X 8
DUAL CHIP ENABLE
CMOS STATIC RAM
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
– 32-Pin 400 or 600 mil Ceramic DIP
– 32-Pin 300 mil Ceramic SOJ
– 32-Pin Ceramic LCC (400x820 mil) [2-sided]
– 32-Pin Ceramic LCC (450x550 mil)
– 32-Pin Solder Seal Ceramic Flatpack
– 32-Pin 600 mil Plastic DIP
– 32-Pin 400 mil Plastic SOJ
FEATURES
Access Times
– 17/20/25/35/45/55/70 ns
Single 5V±10% Power Supply
Easy Memory Expansion using
CE
1
,
CE
2
,
and
OE
Inputs
Battery Backup: 2V Data Retention
[P4C1024L only]
Common Data I/O
Three-State Outputs
DESCRIPTION
The P4C1024/L is a 1,048,576-bit high speed CMOS static
RAM organized as 128K x 8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply.
Access times of 17 ns to 70 ns are available. CMOS is
utlilized to reduce power consumption to a low level.
The P4C1024/L device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
16
. Reading is ac-
complished by device selection (CE
1
low and CE
2
high)
and output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these conditions,
the data in the addressed memory location is presented
on the data input/output pins. The input/output pins stay
in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW. The low power version offers 2V data
retention mode.
The P4C1024/L is packaged in a 32-pin 400 or 600 mil
ceramic DIP and in a 32-pin ceramic SOJ.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (C10, C11), CERAMIC SOJ (CJ-7),
SOLDER SEAL FLATPACK (FS-3), LCC (L1)
LCC (L6)
Document #
SRAM124
REV 13
Revised Mar 2021
P4C1024 - HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM
MAXIMUM RATINGS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +6
-0.5 to V
CC
+ 0.5
-55 to +125
-55 to +125
-65 to +150
1.0
20
Unit
V
V
°C
°C
°C
W
mA
RECOMMENDED OPERATING CONDITIONS
Grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Typ
8
10
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
Parameter
Output High Voltage (I/O
0
-I/O
7
)
Output Low Voltage (I/O
0
-I/O
7
)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
Current
TTL Standby Current
(TTL Input Levels)
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
(Over Recommended Operating Temperature & Supply Voltage)
Test Conditions
I
OH
= -4mA, V
CC
=4.5V
I
OL
= 6mA
Com/Ind
Military
Min
2.4
Max
Unit
V
0.40
0.55
2.2
-0.5
V
CC
+ 0.5
0.8
10
10
33
V
V
V
µA
µA
mA
GND ≤ V
IN
≤ V
CC
GND ≤ V
OUT
≤ V
CC
,
CE
1
=V
IH
CE
1
≥ V
IH
or CE
2
≤ V
IL
,
V
CC
=Max, f=0, Outputs Open
CE
1
≥ V
HC
or CE
2
≤ V
LC
,
V
CC
=Max,f=0, Outputs Open,
V
IN
≤ V
LC
or V
IN
≥ V
HC
-10
-10
I
SB1
17
mA
N/A = Not applicable
Document #
SRAM124
REV 13
Page 2
P4C1024 - HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter
I
CC
Dynamic Operating Current
Temperature
Commercial
Industrial
Military
-17
100
110
125
-20
90
100
110
-25
85
95
105
-35
80
90
100
-45
N/A
85
95
-55
N/A
N/A
90
-70
N/A
N/A
85
Unit
mA
mA
mA
DATA RETENTION CHARACTERISTICS (P4C1024L ONLY)
Symbol Parameter
V
DR
I
CCDR
t
CDR
t
R†
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time CE
2
≤ 0.2V, V
IN
≥ V
CC
– 0.2V
Operation Recovery Time
or V
IN
≤ 0.2V
CE
1
≥ V
CC
– 0.2V,
Test Conditions
Min
2.0
325
0
t
RC§
530
6,000
9,000
Typ* V
CC
=
2.0V
3.0V
Max V
CC
=
2.0V
3.0V
Unit
V
µA
ns
ns
§ t
RC
= Read Cycle Time
† This Parameter is guaranteed but not tested
* T
A
= +25°C
DATA RETENTION WAVEFORM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address
Change
Chip Enable to Output in
Low Z
Chip Disable to Output in
High Z
Output Enable Low to Data
Valid
Output Enable Low to Low Z
Output Enable High to High
Z
Chip Enable to Power Up
Time
Chip Disable to Power Down
Time
0
17
0
9
0
20
3
3
10
10
0
10
0
25
-17
Min
Max
Min
-20
Max
Min
-25
Max
Min
-35
Max
Min
-45
Max
Min
-55
Max
Min
-70
Max
Unit
17
17
17
20
20
20
3
3
12
12
25
25
25
3
3
13
13
0
12
35
35
35
3
3
15
15
0
15
0
35
45
45
45
3
3
20
20
0
20
0
45
55
55
55
3
3
25
25
0
25
0
55
70
70
70
3
3
30
30
0
30
0
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM124
REV 13
Page 3
P4C1024 - HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,7,8)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
1
,
CE
2
CONTROLLED)
(5, 7, 10)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to
MAXIMUM rating condi-
tions for extended periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet
per minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
WE
is HIGH for READ cycle.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW and CE
2
transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9.
Read Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether
CE
1
or CE
2
causes them.
5.
6.
7.
Document #
SRAM124
REV 13
Page 4
P4C1024 - HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
-17
Min
Max
-20
Min
Max
-25
Min
Max
-35
Min
Max
-45
Min
Max
-55
Min
Max
-70
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
14
14
0
14
0
9
0
8
3
20
15
15
0
15
0
10
0
9
3
25
20
20
0
20
0
15
0
10
3
35
25
25
0
25
0
20
0
15
3
45
35
35
0
35
0
30
0
20
3
55
40
40
0
40
0
35
0
25
3
70
45
45
0
45
0
40
0
30
3
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(11)
Notes:
11. CE
1
and
WE
must be LOW, and CE
2
HIGH for WRITE cycle.
12. OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
13. If
CE
1
goes HIGH, or CE
2
goes LOW, simultaneously with
WE
HIGH,
the output remains in a high impedance state
14. Write Cycle Time is measured from the last valid address to the
first transitioning address.
Document #
SRAM124
REV 13
Page 5
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