PIC32MZ Embedded
Connectivity (EC) Family
32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with
Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog
Operating Conditions
• 2.3V to 3.6V, -40ºC to +85ºC, DC to 200 MHz
• 2.3V to 3.6V, -40ºC to +105ºC, DC to 180 MHz
• 2.3V to 3.6V, -40ºC to +125ºC (Planned)
Advanced Analog Features
•
•
•
•
10-bit ADC resolution and up to 48 analog inputs
Flexible and independent ADC trigger sources
Two comparators with 32 programmable voltage references
Temperature sensor with ±2ºC accuracy
Core: 200 MHz (up to 330 DMIPS) microAptiv™
16 KB I-Cache, 4 KB D-Cache
MMU for optimum embedded OS execution
microMIPS™ mode for up to 35% smaller code size
DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating and fractional math
• Code-efficient (C and Assembly) architecture
•
•
•
•
Communication Interfaces
• Two CAN modules (with dedicated DMA channels):
- 2.0B Active with DeviceNet™ addressing support
• Six UART modules (25 Mbps):
- Supports LIN 1.2 and IrDA
®
protocols
• Six 4-wire SPI modules
• SQI configurable as an additional SPI module (50 MHz)
• Five I
2
C modules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
• Peripheral Pin Select (PPS) to enable function remap
Clock Management
•
•
•
•
0.9% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timers (WDT) and Deadman
Timer (DMT)
• Fast wake-up and start-up
Timers/Output Compare/Input Capture
•
•
•
•
•
Nine 16-bit or up to four 32-bit timers/counters
Nine Output Compare (OC) modules
Nine Input Capture (IC) modules
PPS to enable function remap
Real-Time Clock and Calendar (RTCC) module
Power Management
• Low-power modes (Sleep and Idle)
• Integrated Power-on Reset and Brown-out Reset
Input/Output
• 5V-tolerant pins with up to 32 mA source/sink
• Selectable open drain, pull-ups, and pull-downs
• External interrupts on all I/O pins
Memory Interfaces
• 50 MHz External Bus Interface (EBI)
• 50 MHz Serial Quad Interface (SQI)
Audio and Graphics Interfaces
•
•
•
•
Graphics interfaces: EBI or PMP
Audio data communication: I
2
S, LJ, and RJ
Audio control interfaces: SPI and I
2
C™
Audio master clock: Fractional clock frequencies with USB
synchronization
Qualification and Class B Support
•
•
•
•
AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) Planned
AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) Planned
Class B Safety Library, IEC 60730
Back-up internal oscillator
Debugger Development Support
•
•
•
•
•
In-circuit and in-application programming
4-wire MIPS
®
Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
High-Speed (HS) Communication Interfaces
(with Dedicated DMA)
• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface
Security Features
• Crypto Engine with a RNG for data encryption/decryption
and authentication (AES, 3DES, SHA, MD5, and HMAC)
• Advanced memory protection:
- Peripheral and memory region access control
Software and Tools Support
•
•
•
•
•
C/C++ compiler with native DSP/fractional support
MPLAB
®
Harmony Integrated Software Framework
TCP/IP, USB, Graphics, and mTouch™ middleware
MFi, Android™, and Bluetooth
®
audio frameworks
FreeRTOS™, OPENRTOS
®
,
μC/OS™,
and other popular
RTOS kernels
Direct Memory Access (DMA)
• Eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
Packages
Type
Pin Count
I/O Pins (up to)
Contact/Lead Pitch
Dimensions
QFN
64
53
0.50 mm
9x9x0.9 mm
64
53
0.50 mm
10x10x1 mm
TQFP
100
78
0.40 mm
12x12x1 mm
0.50 mm
14x14x1 mm
144
120
0.40 mm
16x16x1 mm
VTLA
124
98
0.50 mm
9x9x0.9 mm
LQFP
144
120
0.50 mm
20x20x1.40 mm
2013-2014 Microchip Technology Inc.
Preliminary
DS60001191C-page 1
PIC32MZ Embedded Connectivity (EC) Family
Device Pin Tables
TABLE 3:
PIN NAMES FOR 64-PIN DEVICES
64-PIN QFN
(4)
AND TQFP (TOP VIEW)
PIC32MZ0512EC(E/F/K)064
PIC32MZ1024EC(G/H/M)064
PIC32MZ1024EC(E/F/K)064
PIC32MZ2048EC(G/H/M)064
M
64
1
64
QFN
(4)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note
Full Pin Name
AN17/ETXEN/RPE5/PMD5/RE5
AN16/ETXD0/PMD6/RE6
AN15/ETXD1/PMD7/RE7
AN14/C1IND/RPG6/SCK2/PMA5/RG6
AN13/C1INC/RPG7/SDA4/PMA4/RG7
AN12/C2IND/RPG8/SCL4/PMA3/RG8
V
SS
V
DD
MCLR
AN11/C2INC/RPG9/PMA2/RG9
AN45/C1INA/RPB5/RB5
AN4/C1INB/RB4
AN3/C2INA/RPB3/RB3
AN2/C2INB/RPB2/RB2
PGEC1/V
REF
-/CV
REF
-/AN1/RPB1/RB1
PGED1/V
REF
+/CV
REF
+/AN0/RPB0/PMA6/RB0
PGEC2/AN46/RPB6/RB6
PGED2/AN47/RPB7/RB7
AV
DD
AVss
AN48/RPB8/PMA10/RB8
AN49/RPB9/PMA7/RB9
TMS/CV
REFOUT
/AN5/RPB10/PMA13/RB10
TDO/AN6/PMA12/RB11
V
SS
V
DD
TCK/AN7/PMA11/RB12
TDI/AN8/RB13
AN9/RPB14/SCK3/PMA1/RB14
AN10/EMDC/AEMDC/RPB15/OCFB/PMA0/RB15
OSC1/CLKI/RC12
OSC2/CLKO/RC15
1:
2:
3:
4:
Pin #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
V
BUS
V
USB3V3
V
SS
D-
D+
USBID/RPF3/RF3
V
DD
V
SS
RPF4/SDA5/PMA9/RF4
RPF5/SCL5/PMA8/RF5
1
TQFP
Full Pin Name
AERXD0/ETXD2/RPD9/SDA1/PMCS2/PMA15/RD9
ECOL/RPD10/SCL1/SCK4/RD10
AERXCLK/AEREFCLK/ECRS/RPD11/PMCS1/PMA14/RD11
AERXD1/ETXD3/RPD0/RTCC/INT0/RD0
SOSCI/RPC13/RC13
SOSCO/RPC14/T1CK/RC14
EMDIO/AEMDIO/RPD1/SCK1/RD1
ETXERR/AETXEN/RPD2/SDA3/RD2
AERXERR/ETXCLK/RPD3/SCL3/RD3
SQICS0/RPD4/PMWR/RD4
SQICS1/RPD5/PMRD/RD5
V
DD
V
SS
ERXD3/AETXD1/RPF0/RF0
TRCLK/SQICLK/ERXD2/AETXD0/RPF1/RF1
TRD0/SQID0/ERXD1/PMD0/RE0
V
SS
V
DD
TRD1/SQID1/ERXD0/PMD1/RE1
TRD2/SQID2/ERXDV/ECRSDV/AECRSDV/PMD2/RE2
TRD3/SQID3/ERXCLK/EREFCLK/RPE3/PMD3/RE3
AN18/ERXERR/PMD4/RE4
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
Section 12.3 “Peripheral Pin
Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See
Section 12.0 “I/O Ports”
for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V
SS
externally.
DS60001191C-page 4
Preliminary
2013-2014 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 4:
PIN NAMES FOR 100-PIN DEVICES
100-PIN TQFP (TOP VIEW)
PIC32MZ0512EC(E/F/K)100
PIC32MZ1024EC(G/H/M)100
PIC32MZ1024EC(E/F/K)100
PIC32MZ2048EC(G/H/M)100
M
100
1
Pin #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
V
SS
V
DD
TCK/EBIA19/AN29/RA1
TDI/EBIA18/AN30/RPF13/SCK5/RF13
TDO/EBIA17/AN31/RPF12/RF12
EBIA11/AN7/ERXD0/AECRS/PMA11/RB12
AN8/ERXD1/AECOL/RB13
EBIA1/AN9/ERXD2/AETXD3/RPB14/SCK3/PMA1/RB14
EBIA0/AN10/ERXD3/AETXD2/RPB15/OCFB/PMA0/RB15
V
SS
V
DD
AN32/AETXD0/RPD14/RD14
AN33/AETXD1/RPD15/SCK6/RD15
OSC1/CLKI/RC12
OSC2/CLKO/RC15
V
BUS
V
USB3V3
V
SS
D-
D+
USBID/RPF3/RF3
EBIRDY3/RPF2/SDA3/RF2
EBIRDY2/RPF8/SCL3/RF8
EBICS0/SCL2/RA2
EBIRDY1/SDA2/RA3
EBIA14/PMCS1/PMA14/RA4
V
DD
V
SS
EBIA9/RPF4/SDA5/PMA9/RF4
EBIA8/RPF5/SCL5/PMA8/RF5
AETXCLK/RPA14/SCL1/RA14
AETXEN/RPA15/SDA1/RA15
EBIA15/RPD9/PMCS2/PMA15/RD9
RPD10/SCK4/RD10
EMDC/AEMDC/RPD11/RD11
Full Pin Name
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Note
Full Pin Name
AN23/AERXERR/RG15
EBIA5/AN34/PMA5/RA5
EBID5/AN17/RPE5/PMD5/RE5
EBID6/AN16/PMD6/RE6
EBID7/AN15/PMD7/RE7
EBIA6/AN22/RPC1/PMA6/RC1
EBIA12/AN21/RPC2/PMA12/RC2
EBIWE/AN20/RPC3/PMWR/RC3
EBIOE/AN19/RPC4/PMRD/RC4
AN14/C1IND/ECOL/RPG6/SCK2/RG6
EBIA4/AN13/C1INC/ECRS/RPG7/SDA4/PMA4/RG7
EBIA3/AN12/C2IND/ERXDV/ECRSDV/AERXDV/
AECRSDV/RPG8/SCL4/PMA3/RG8
V
SS
V
DD
MCLR
EBIA2/AN11/C2INC/ERXCLK/EREFCLK/AERXCLK/
AEREFCLK/RPG9/PMA2/RG9
TMS/EBIA16/AN24/RA0
AN25/AERXD0/RPE8/RE8
AN26/AERXD1/RPE9/RE9
AN45/C1INA/RPB5/RB5
AN4/C1INB/RB4
AN3/C2INA/RPB3/RB3
AN2/C2INB/RPB2/RB2
PGEC1/AN1/RPB1/RB1
PGED1/AN0/RPB0/RB0
PGEC2/AN46/RPB6/RB6
PGED2/AN47/RPB7/RB7
V
REF
-/CV
REF
-/AN27/AERXD2/RA9
V
REF
+/CV
REF
+/AN28/AERXD3/RA10
AV
DD
AV
SS
EBIA10/AN48/RPB8/PMA10/RB8
EBIA7/AN49/RPB9/PMA7/RB9
EBIA13/CV
REFOUT
/AN5/RPB10/PMA13/RB10
AN6/ERXERR/AETXERR/RB11
1:
2:
3:
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
Section 12.3 “Peripheral Pin
Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See
Section 12.0 “I/O Ports”
for more
information.
Shaded pins are 5V tolerant.
2013-2014 Microchip Technology Inc.
Preliminary
DS60001191C-page 5
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