MCF5407 ColdFire
®
Integrated Microprocessor
User’s Manual
MCF5407UM/D
Rev. 0.1, 11/2001
ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc.
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2
C is a registered trademark of Philips Semiconductors
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Overview
Part I: MCF5407 Processor Core
ColdFire Core
Hardware Multiply/Accumulate (MAC) Unit
Local Memory
Debug Support
Part II: System Integration Module (SIM)
SIM Overview
Phase-Locked Loop (PLL)
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2
C Module
Interrupt Controller
Chip-Select Module
Synchronous/Asynchronous DRAM Controller Module
Part III: Peripheral Module
DMA Controller Module
Timer Module
UART Modules
1
Part I
2
3
4
5
Part II
6
7
8
9
10
11
Part III
12
13
14
Parallel Port (General-Purpose I/O)
Part IV: Hardware Interface
Mechanical Data
Signal Descriptions
Bus Operation
IEEE 1149.1 Test Access Port (JTAG)
Electrical Specifications
Appendix A: Migration
Appendix B: Memory Map
Glossary of Terms and Abbreviations
Index
15
Part IV
16
17
18
19
20
A
B
GLO
IND
1
Part I
2
3
4
5
Part II
6
7
8
9
10
11
Part III
12
13
14
Overview
Part I: MCF5407 Processor Core
ColdFire Core
Hardware Multiply/Accumulate (MAC) Unit
Local Memory
Debug Support
Part II: System Integration Module (SIM)
SIM Overview
Phase-Locked Loop (PLL)
I
2
C Module
Interrupt Controller
Chip-Select Module
Synchronous/Asynchronous DRAM Controller Module
Part III: Peripheral Module
DMA Controller Module
Timer Module
UART Modules
15
Part IV
16
17
18
19
20
A
B
GLO
IND
Parallel Port (General-Purpose I/O)
Part IV: Hardware Interface
Mechanical Data
Signal Descriptions
Bus Operation
IEEE 1149.1 Test Access Port (JTAG)
Electrical Specifications
Appendix A: Migration
Appendix B: Memory Map
Glossary of Terms and Abbreviations
Index
CONTENTS
Paragraph
Number
Title
Page
Number
Chapter 1
Overview
1.1
1.2
1.2.1
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.2
1.3.2.1
1.3.2.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.8.1
1.3.8.2
1.3.8.3
1.3.8.4
1.3.8.5
1.3.9
1.3.10
1.4
1.4.1
1.4.2
Features ............................................................................................................... 1-1
MCF5407 Features.............................................................................................. 1-4
Process ............................................................................................................ 1-7
ColdFire Module Description ............................................................................. 1-7
ColdFire Core ................................................................................................. 1-7
Instruction Fetch Pipeline (IFP).................................................................. 1-7
Operand Execution Pipeline (OEP) ............................................................ 1-8
MAC Module.............................................................................................. 1-8
Integer Divide Module................................................................................ 1-8
Harvard Architecture ...................................................................................... 1-8
16-Kbyte Instruction Cache/8-Kbyte Data Cache ...................................... 1-9
Internal 2-Kbyte SRAMs ............................................................................ 1-9
DRAM Controller ........................................................................................... 1-9
DMA Controller.............................................................................................. 1-9
UART Modules............................................................................................. 1-10
Timer Module ............................................................................................... 1-11
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C Module ................................................................................................... 1-11
System Interface ........................................................................................... 1-11
External Bus Interface .............................................................................. 1-11
Chip Selects .............................................................................................. 1-11
16-Bit Parallel Port Interface .................................................................... 1-12
Interrupt Controller ................................................................................... 1-12
JTAG......................................................................................................... 1-12
System Debug Interface................................................................................ 1-12
PLL Module.................................................................................................. 1-13
Programming Model, Addressing Modes, and Instruction Set......................... 1-13
Programming Model ..................................................................................... 1-15
User Registers ............................................................................................... 1-15
Contents
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