1. Stratix III Device Family Overview
SIII51001-1.8
The Stratix
®
III family provides one of the most architecturally advanced,
high-performance, low-power FPGAs in the marketplace.
Stratix III FPGAs lower power consumption through Altera’s innovative
Programmable Power Technology, which provides the ability to turn on the
performance where needed and turn down the power consumption for blocks not in
use. Selectable Core Voltage and the latest in silicon process optimizations are also
employed to deliver the industry’s lowest power, high-performance FPGAs.
Specifically designed for ease of use and rapid system integration, the Stratix III
FPGA family offers two variants optimized to meet different application needs:
■
The Stratix III
L
family provides balanced logic, memory, and multiplier ratios for
mainstream applications.
The Stratix III
E
family is memory- and multiplier-rich for data-centric
applications.
■
Modular I/O banks with a common bank structure for vertical migration lend
efficiency and flexibility to the high-speed I/O. Package and die enhancements with
dynamic on-chip termination, output delay, and current strength control provide
best-in-class signal integrity.
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a
programmable alternative to custom ASICs and programmable processors for
high-performance logic, digital signal processing (DSP), and embedded designs.
Stratix III devices include optional configuration bit stream security through volatile
or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where
ultra-high reliability is required, Stratix III devices include automatic error detection
circuitry to detect data corruption by soft errors in the configuration random-access
memory (CRAM) and user memory cells.
Features Summary
Stratix III devices offer the following features:
■
■
48,000 to 338,000 equivalent logic elements (LEs) ( refer to
Table 1–1)
2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM
block sizes to implement true dual-port memory and FIFO buffers
High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18,
and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for
robust signal integrity
Programmable Power Technology, which minimizes power while maximizing
device performance
■
■
■
© March 2010
Altera Corporation
Stratix III Device Handbook, Volume 1
1–2
Chapter 1: Stratix III Device Family Overview
Features Summary
■
Selectable Core Voltage, available in low-voltage devices (L ordering code suffix),
enables selection of lowest power or highest performance operation
Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration,
clock switchover, programmable bandwidth, clock synthesis, and dynamic phase
shifting
Memory interface support with dedicated DQS logic on all I/O banks
Support for high-speed external memory interfaces including DDR, DDR2,
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular
I/O banks
Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide
range of industry I/O standards
Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O
banks
High-speed differential I/O support with serializer/deserializer (SERDES) and
dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance
Support for high-speed networking and communications bus standards including
SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
The only high-density, high-performance FPGA with support for 256-bit AES
volatile and non-volatile security key to protect designs
Robust on-chip hot socketing and power sequencing support
Integrated cyclical redundancy check (CRC) for configuration memory error
detection with critical error determination for high availability systems support
Built-in error correction coding (ECC) circuitry to detect and correct data errors in
M144K TriMatrix memory blocks
Nios
®
II embedded processor support
Support for multiple intellectual property megafunctions from Altera
®
MegaCore
®
functions and Altera Megafunction Partners Program (AMPP
SM
)
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Stratix III Device Handbook, Volume 1
© March 2010
Altera Corporation
Chapter 1: Stratix III Device Family Overview
Features Summary
1–3
Table 1–1
lists the Stratix III FPGA family features.
Table 1–1.
FPGA Family Features for Stratix III Devices
Device/
Feature
EP3SL50
EP3SL70
Stratix III
Logic
Family
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
Stratix III
Enhanced
Family
EP3SE80
EP3SE110
EP3SE260
Notes to
Table 1–1:
(1) MLAB ROM mode supports twice the number of MLAB RAM Kbits.
(2) For total ROM Kbits, use this equation to calculate:
Total ROM Kbits = Total Embedded RAM Kbits + [(# of MLAB blocks × 640)/1024]
(3) The availability of the PLLs shown in this column is based on the device with the largest package. Refer to the
Clock Networks and PLLs in Stratix
III Devices
chapter in volume 1 of the
Stratix III Device Handbook
for the availability of the PLLs for each device.
ALMs
LEs
M9K
Blocks
108
150
275
355
468
1,040
400
495
639
864
M144K
Blocks
6
6
12
16
36
48
12
12
16
48
Total
MLAB
Embedded
Blocks
RAM Kbits
950
1,350
2,150
2,850
4,000
6,750
950
1,600
2,150
5,100
1,836
2,214
4,203
5,499
9,396
16,272
5,328
6,183
8,055
14,688
MLAB
RAM
Kbits
(1)
297
422
672
891
1,250
2,109
297
500
672
1,594
Total
RAM
Kbits(2)
2,133
2,636
4,875
6,390
10,646
18,381
5,625
6,683
8,727
16,282
18×18-bit
Multipliers
(FIR Mode)
216
288
288
384
576
576
384
672
896
768
PLLs
(3)
4
4
8
8
12
12
4
8
8
12
19K
27K
43K
57K
80K
135K
19K
32K
43K
102K
47.5K
67.5K
107.5K
142.5K
200K
337.5K
47.5K
80K
107.5K
255K
The Stratix III logic family (L) offers balanced logic, memory, and multipliers to
address a wide range of applications, while the enhanced family (E) offers more
memory and multipliers per logic and is ideal for wireless, medical imaging, and
military applications.
Stratix III devices are available in space-saving FineLine BGA (FBGA) packages (refer
to
Table 1–2
and
Table 1–3).
© March 2010
Altera Corporation
Stratix III Device Handbook, Volume 1
1–4
Chapter 1: Stratix III Device Family Overview
Features Summary
Table 1–2
lists the Stratix III FPGA package options and I/O pin counts.
Table 1–2.
Package Options and I/O Pin Counts
(Note 1)
Device
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Notes to
Table 1–2:
(1) The arrows indicate vertical migration.
(2) All I/O pin counts include eight dedicated clock inputs (CLK1p,
CLK1n, CLK3p, CLK3n, CLK8p, CLK8n,
CLK10p,
and
CLK10n)
that can be used for data inputs.
(3) All I/O pin counts include eight dedicated clock inputs (CLK1p,
CLK1n, CLK3p, CLK3n, CLK8p,
CLK8n, CLK10p,
and
CLK10n)
and eight dedicated corner PLL clock inputs (PLL_L1_CLKp,
PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp,
and
PLL_R1_CLKn)
that can be used for data inputs.
(4) The EP3SL340 FPGA is offered only in the H1152 package, but not offered in the F1152 package.
(5) The EP3SE260 and EP3SL200 FPGAs are offered only in the H780 package, but not offered in the F780 package.
484-Pin
FineLine
BGA
(2)
296
296
—
—
—
—
296
—
—
—
780-Pin
FineLine
BGA
(2)
488
488
488
488
488
(5)
—
488
488
488
488
(5)
1152-Pin
FineLine
BGA
(2)
—
—
744
744
744
744
(4)
—
744
744
744
1517-Pin
FineLine BGA
(3)
—
—
—
—
976
976
—
—
—
976
1760-Pin
FineLine BGA
(3)
—
—
—
—
—
1,120
—
—
—
—
All Stratix III devices support vertical migration within the same package (for
example, you can migrate between the EP3SL50 and EP3SL70 devices in the 780-pin
FineLine BGA package). Vertical migration allows you to migrate to devices whose
dedicated pins, configuration pins, and power pins are the same for a given package
across device densities.
To ensure that a board layout supports migratable densities within one package
offering, enable the applicable vertical migration path within the Quartus
®
II
software. On the Assignments menu, point to
Device
and click
Migration Devices.
You can migrate from the
L
family to the
E
family without increasing the number of
LEs available. This minimizes the cost of vertical migration.
Table 1–3
lists the Stratix III FineLine BGA (FBGA) package sizes.
Table 1–3.
FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm
2
)
Length/Width (mmmm)
484 Pin
1.00
529
23/23
780 Pin
1.00
841
29/29
1152 Pin
1.00
1,225
35/35
1517 Pin
1.00
1,600
40/40
1760 Pin
1.00
1,849
43/43
Stratix III Device Handbook, Volume 1
© March 2010
Altera Corporation
Chapter 1: Stratix III Device Family Overview
Features Summary
1–5
Table 1–4
lists the Stratix III Hybrid FineLine BGA (HBGA) package sizes.
Table 1–4.
Hybrid FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm
2
)
Length/Width (mmmm)
780 Pin
1.00
1,089
33/33
1152 Pin
1.00
1,600
40/40
Stratix III devices are available in up to three speed grades: –2, –3, and –4, with –2
being the fastest. Stratix III devices are offered in both commercial and industrial
temperature range ratings with leaded and lead-free packages. Selectable Core
Voltage is available in specially marked low-voltage devices (L ordering code suffix).
Table 1–5
lists the Stratix III device speed grades.
Table 1–5.
Speed Grades for Stratix III Devices (Part 1 of 2)
Temperature
Grade
484 -Pin
FineLine
BGA
–2, –3, –4,
–4L
–3, –4, –4L
–2, –3, –4,
–4L
–3, –4, –4L
—
—
—
—
—
—
—
—
–2, –3, –4,
–4L
–3, –4, –4L
—
—
—
—
Device
780-Pin
FineLine
BGA
–2, –3,–4,
–4L
–3, –4, –4L
–2, –3, –4,
–4L
–3, –4, –4L
–2, –3, –4,
–4L
–3, –4, –4L
–2,–3, –4,
–4L
–3, –4, –4L
—
—
—
—
–2, –3, –4,
–4L
–3, –4, –4L
–2, –3, –4,
–4L
–3, –4, –4L
–2,–3, –4,
–4L
–3, –4, –4L
780-Pin
Hybrid
FineLine
BGA
—
—
—
—
—
—
—
—
–2,–3, –4,
–4L
–3, –4, –4L
—
—
—
—
—
—
—
—
1152-Pin
FineLine
BGA
—
—
—
—
–2, –3, –4,
–4L
–3, –4, –4L
–2, –3, –4,
–4L
–3, –4, –4L
–2,–3, –4,
–4L
–3, –4, –4L
—
—
—
—
–2, –3, –4,
–4L
–3, –4, –4L
–2, –3, –4,
–4L
–3, –4, –4L
1152-Pin
Hybrid
FineLine
BGA
—
—
—
—
—
—
—
—
—
—
–2, –3, –4
–3, –4, –4L
—
—
—
—
—
—
1517-Pin
FineLine
BGA
—
—
—
—
—
—
—
—
–2,–3, –4,
–4L
–3, –4, –4L
–2, –3, –4
–3, –4, –4L
—
—
—
—
—
—
1760-Pin
FineLine
BGA
—
—
—
—
—
—
—
—
—
—
–2, –3, –4
–3, –4, –4L
—
—
—
—
—
—
EP3SL50
Commercial
Industrial
EP3SL70
Commercial
Industrial
EP3SL110
Commercial
Industrial
EP3SL150
Commercial
Industrial
EP3SL200
Commercial
Industrial
(1)
EP3SL340
Commercial
Industrial
(1)
Commercial
Industrial
EP3SE50
EP3SE80
Commercial
Industrial
EP3SE110
Commercial
Industrial
© March 2010
Altera Corporation
Stratix III Device Handbook, Volume 1
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