Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806:
Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Part Number
MC68HC908JW32
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9RS08LA8
MC9S08GT16A
MC9S908QE32
MC9S908QE8
MC9S08JS16
MC9S08QB8
MC9S08QG8
MC9S08SH8
MC9RS08KB12
MC9S08QG8
MC9RS08KB12
MC9S08QG8
MC9RS08KA2
6 DFN
Package Description
48 QFN
Original (gold wire)
Current (copper wire)
package document number package document number
98ARH99048A
98ASA00466D
48 QFN
32 QFN
32 QFN
32 QFN
24 QFN
98ARL10606D
98ARH99035A
98ARE10566D
98ASA00071D
98ARL10608D
98ASA00466D
98ASA00473D
98ASA00473D
98ASA00736D
98ASA00734D
24 QFN
24 QFN
24 QFN
16 QFN
8 DFN
98ARL10605D
98ARE10714D
98ASA00087D
98ARE10614D
98ARL10557D
98ASA00474D
98ASA00474D
98ASA00602D
98ASA00671D
98ASA00672D
98ARL10602D
98ASA00735D
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9RS08KB12
Rev. 5, 1/2012
MC9RS08KB12
MC9RS08KB12 Series
Covers:MC9RS08KB12
MC9RS08KB8
MC9RS08KB4
MC9RS08KB2
• 8-Bit RS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 1.8 V to 5.5 V across temperature
range of –40 °C to 85 °C
– Subset of HC08 instruction set with added BGND
instruction
– Single Global interrupt vector
• On-Chip Memory
– Up to 12 KB flash read/program/erase over full
operating voltage and temperature,
12 KB/8 KB/4 KB/2 KB flash are optional
– Up to 254-byte random-access memory (RAM),
254-byte/126-byte RAM are optional
– Security circuitry to prevent unauthorized access to flash
contents
• Power-Saving Modes
– Wait mode — CPU shuts down; system clocks continue
to run; full voltage regulation
– Stop mode — CPU shuts down; system clocks are
stopped; voltage regulator in standby
– Wakeup from power-saving modes using RTI, KBI,
ADC, ACMP, SCI and LVD
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
39.0625 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution
and 2% deviation over temperature and voltage;
supporting bus frequencies up to 10 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1 kHz internal low
power oscillator
– Low-voltage detection with reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash-block protection
20-Pin SOIC
Case 751D
16-Pin TSSOP
Case 948F
24-Pin QFN
Case 1982-01
16-Pin SOIC N/B
Case 751B
8-Pin SOIC
Case 751
8-Pin DFN
Case 1452-02
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• Peripherals
–
ADC
— 12-channel, 10-bit resolution; 2.5
μs
conversion time; automatic compare function;
1.7
mV/°C temperature sensor; internal bandgap
reference channel; operation in stop; hardware trigger
–
ACMP
— Analog comparator; full rail-to-rail supply
operation; option to compare to fixed internal bandgap
reference voltage; can operate in stop mode
–
TPM
— One 2-channel timer/pulse-width modulator
module; selectable input capture, output compare, or
buffered edge- or center-aligned PWM on each channel
–
IIC
— Inter-integrated circuit bus module capable of
operation up to 100 kbps with maximum bus loading;
capable of higher baud rates with reduced loading
–
SCI
— One serial communications interface module
with optional 13-bit break; LIN extensions
–
MTIM
— Two 8-bit modulo timers; optional clock
sources
–
RTI
— One real-time clock with optional clock sources
–
KBI
— Keyboard interrupts; up to 8 ports
• Input/Output
– 18 GPIOs in 24- and 20-pin packages; 14 GPIOs in 16-pin
package; 6 GPIOs in 8-pin package; including one
output-only pin and one input-only pin
– Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins
• Package Options
– MC9RS08KB12/MC9RS08KB8/MC9RS08KB4
— 24-pin QFN, 20-pin SOIC, 16-pin SOIC NB or
TSSOP
– MC9RS08KB2
— 8-pin SOIC or DFN
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2012. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5 ESD Protection and Latch-Up Immunity. . . . . . . . . . . . . 8
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . 23
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . . 26
3.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.9.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . .28
3.10 Analog Comparator (ACMP) Electrical . . . . . . . . . . . . .28
3.11 Internal Clock Source Characteristics. . . . . . . . . . . . . .29
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .35
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Date
Description of Changes
1
2
3
4/13/2009
5/22/2009
8/31/2009
Updated on shared review comments, added package information.
Completed most of the TBDs, corrected the block diagram.
Completed all the TBDs.
Changed V
LVD
and added R
PD
in the
Table 7.
Changed SI
DD
,
ADC adder from stop, RTI adder from stop with 1 kHz clock source
enabled and LVI adder from stop at 5 V
in the
Table 8
.
Split the 10-Bit ADC Characteristics to
Table 15
and
Table 16
for the V
DDAD
ranges.
Corrected the note 4 in the
Table 8.
Added 24-pin QFN package.
4
5
6/23/2011
1/30/2012
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9RS08KB12RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9RS08KB12 Series MCU Data Sheet, Rev. 5
2
Freescale Semiconductor
MCU Block Diagram
1
V
DD
V
SS
MCU Block Diagram
V
REFH
V
REFL
V
DDAD
V
SSAD
12-CH 10-BIT
ANALOG-TO-DIGITAL
CONVERTER(ADC)
ANALOG COMPARATOR
(ACMP)
RS08 CORE
8-BIT KEYBOARD
CPU
BDC
INTERRUPT(KBI)
SERIAL COMMUNICATION
INTERFACE (SCI)
2-CH TIMER/PWM
MODULE (TPM)
MODULO TIMER
WAKEUP
V
PP
LVD
(MTIM1)
MODULO TIMER
(MTIM2)
INTER-INTEGRATED
CIRCUIT MODULE (IIC)
TxD
RxD
The block diagram,
Figure 1,
shows the structure of the MC9RS08KB12 MCU.
ADP[3:0]
ADP[7:4]
ADP[11:8]
ACMP+
ACMP-
ACMPO
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA1/KBIP1/TPMCH1/ADP1/ACMP–
PORT A
KBIP[3:0]
KBIP[7:4]
PTA2/KBIP2/SDA/RxD/ADP2
PTA3/KBIP3/SCL/TxD/ADP3
PTA4/ACMPO/BKGD/MS
2
PTA5/TCLK/RESET/V
PP1
RESET
RS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
RTI
TPMCH0
TPMCH1
TCLK
TCLK
PTB0/KBIP4/RxD/ADP4
PTB1/KBIP5/TxD/ADP5
PORT B
USER FLASH
MC9RS08KB12 = 12 KB
MC9RS08KB8 = 8 KB
MC9RS08KB4 = 4 KB
MC9RS08KB2 = 2 KB
USER RAM
MC9RS08KB12/KB8 = 254 BYTES
MC9RS08KB4/KB2 = 126 BYTES
20 MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 39.0625 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
TCLK
SCL
SDA
PTB2/KBIP6/ADP6
PTB3/KBIP7/ADP7
PTB4/TPMCH0
PTB5/TPMCH1
PTB6/SDA/XTAL
XTAL
PTB7/SCL/EXTAL
PTC0/ADP8
PORT C
PTC1/ADP9
PTC2/ADP10
PTC3/ADP11
V
DD
V
SS
VOLTAGE REGULATOR
NOTES:
1. PTA5/TCLK/RESET/V
PP
is an input-only pin when used as port pin
2. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin
Figure 1. MC9RS08KB12 Series Block Diagram
2
Pin Assignments
This section shows the pin assignments in the packages available for the MC9RS08KB12 series.
MC9RS08KB12 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor
3
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