Freescale Semiconductor
Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08QE8
Rev. 8, 4/2011
MC9S08QE8
MC9S08QE8 Series
Covers: MC9S08QE8 and
MC9S08QE4
Features
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of
–40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Flash read/program/erase over full operating voltage and
temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
flash contents
• Power-Saving Modes
– Two low power stop modes
– Reduced power wait mode
– Low power run and wait modes allow peripherals to run while
voltage regulator is in standby
– Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents
– Very low power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to real time counter
– 6
s
typical wake-up time from stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to
16 MHz
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of internal reference
allows 0.2% resolution and 2% deviation over temperature and
voltage; supporting bus frequencies from 1 MHz to 10 MHz
• System Protection
– Watchdog computer operating properly (COP) reset with option to
run from dedicated 1 kHz internal clock source or bus clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip debug
module)
32-Pin QFN
Case 2078-01
32-Pin LQFP
Case 873A
28-Pin SOIC
751F-05
20-Pin SOIC
751D-07
16-Pin PDIP
648
16-Pin TSSOP
948F
– On-chip in-circuit emulator (ICE) debug module containing two
comparators and nine trigger modes; eight deep FIFO for storing
change-of-flow addresses and event-only data; debug module
supports both tag and force breakpoints
• Peripherals
–
ADC
— 10-channel, 12-bit resolution; 2.5
s
conversion time;
automatic compare function; 1.7 mV/C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6 V to 1.8 V
–
ACMPx
— Two analog comparators with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal bandgap reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
–
SCI
— Full-duplex non-return to zero (NRZ); LIN master
extended break generation; LIN slave extended break detection;
wake-up on active edge
–
SPI
— Full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or
LSB-first shifting
–
IIC
— Up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven
byte-by-byte data transfer; supporting broadcast mode and 10-bit
addressing
–
TPMx
— Two 3-channel (TPM1 and TPM2); selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel
–
RTC
— (Real-time counter) 8-bit modulus counter with binary or
decimal based prescaler; external clock source for precise time
base, time-of-day, calendar or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for cyclic wakeup
without external components; runs in all MCU modes
• Input/Output
– 26 GPIOs, one output-only pin and one input-only pin
– Eight KBI interrupts with selectable polarity
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
• Package Options
– 32-pin LQFP, 32-pin QFN, 28-pin SOIC, 20-pin SOIC,
16-pin PDIP, 16-pin TSSOP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007-2011. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . 7
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 8
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 8
3.5 ESD Protection and Latch-Up Immunity. . . . . . . 10
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 11
3.7 Supply Current Characteristics. . . . . . . . . . . . . . 14
3.8 External Oscillator (XOSCVLP) Characteristics . 17
3.9 Internal Clock Source (ICS) Characteristics . . . . 18
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 20
3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 20
3.10.2TPM Module Timing. . . . . . . . . . . . . . . . . 21
3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Analog Comparator (ACMP) Electricals. . . . . . . 24
3.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . 25
3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . 29
3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 29
3.14.1Conducted Transient Susceptibility . . . . . 30
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . 31
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
2
3
4
5
Date
Nov 7 2007
Jan 22 2008
March 13 2008
October 8 2008
Description of Changes
Initial preliminary product preview release.
Initial public release.
Added
Figure 11.
Updated the Stop2 and Stop3 mode supply current in the
Table 8.
Replaced the stop mode adders section from
Table 8
with an individual
Table 9
with new
specifications.
Added a footnote to the Min. of the suppply voltage in
Table 7.
Changed the typical value of |I
In
| and |I
OZ
| to — (no typical value) in
Table 7.
Added t
VRR
to
Table 12.
Updated “How to reach us” information.
Updated the operating voltage in
Table 7.
Changed V
DDAD
to V
DDA
, I
DDAD
to I
DDA
, and V
SSAD
to V
SSA
.
In
Table 7,
added |I
OZTOT
|.
In
Table 11,
updated the DCO output frequency range-trimmed, and changed some symbols.
Updated typicals and Max. for
t
IRST.
Updated
Table 17.
Added 32-pin QFN package.
6
7
Nov. 4 2008
April 29 2009
8
April 12, 2011
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08QE8RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08QE8 Series Data Sheet, Rev. 8
2
Freescale Semiconductor
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