Lead-
Free
Package
Options
Available!
ispLSI 1048E
®
In-System Programmable High Density PLD
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
A0
Output Routing Pool
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pin-out Compatible to ispLSI 1048C
TECHNOLOGY
• HIGH PERFORMANCE
—
f
max
= 125 MHz Maximum Operating Frequency
—
t
pd
= 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
E
2
CMOS
®
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
A3
A4
A5
A6
A7
Logic
D Q
D
ES
IG
D Q
D Q
Global Routing Pool (GRP)
Array
GLB
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
N
A2
D5
D4
D3
D2
D1
D0
CLK
0139G1A-isp
Description
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
U
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
SE
— Lead-Free Package Options
is
p
LS
— Synchronous and Asynchronous Clocks
I1
04
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
8E
A
— Reprogram Soldered Devices for Faster Prototyping
The ispLSI 1048E is a High Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1048 archi-
tecture, the ispLSI 1048E device adds two new global
output enable pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
FO
R
N
EW
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
1048e_12
1
Output Routing Pool
A1
D Q
S
D6
D7
Specifications
ispLSI 1048E
Functional Block Diagram
Figure 1. ispLSI 1048E Functional Block Diagram
I/O I/O I/O I/O
95 94 93 92
RESET
GOE 0
GOE 1
I/O I/O I/O I/O
91 90 89 88
I/O I/O I/O I/O
87 86 85 84
I/O I/O I/O I/O
83 82 81 80
IN IN
11 10
I/O I/O I/O I/O
79 78 77 76
I/O I/O I/O I/O
75 74 73 72
I/O I/O I/O I/O
71 70 69 68
I/O I/O I/O I/O
67 66 65 64
IN
9
IN
8
Input Bus
Generic
Logic Blocks
(GLBs)
F7
F6
Output Routing Pool (ORP)
F5
F4
F3
F2
F1
F0
E7
E6
Input Bus
Output Routing Pool (ORP)
E5
E4
E3
E2
D
ES
IG
E1
E0
D7
D6
D5
D4
D3
D2
D1
D0
N
IN 7
IN 6
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
A1
Output Routing Pool (ORP)
EW
lnput Bus
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
N
Global
Routing
Pool
(GRP)
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
A0
FO
R
C0
C1
C2
C3
C4
C5
C6
C7
Clock
Distribution
Network
Output Routing Pool (ORP)
Megablock
Input Bus
ispEN
IN 2
SDO/
IN 3
Output Routing Pool (ORP)
Input Bus
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
48
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
EA
I/O I/O I/O I/O
28 29 30 31
IN SCLK/ I/O I/O I/O I/O
4 IN 5 32 33 34 35
I/O I/O I/O I/O
36 37 38 39
I/O I/O I/O I/O
40 41 42 43
I/O I/O I/O I/O
44 45 46 47
Y Y Y Y
0 1 2 3
0139F(2)-48B-isp
10
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
1048E device contains six Megablocks.
U
SE
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
pL
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.
is
SI
2
S
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
Specifications
ispLSI 1048E
Absolute Maximum Ratings
1
Supply Voltage V
cc
. ................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
EW
D
ES
IG
MIN.
4.75
4.5
0
2.0
MAX.
5.25
5.5
0.8
V
cc
+1
pf
pf
N
N
UNITS
V
V
V
V
Table 2-0005/1048E
Capacitance (T
A
=25
o
C, f=1.0 MHz)
SYMBOL
EA
FO
V
IL
V
IH
R
V
CC
T
A
= 0°C to + 70°C
T
A
= -40°C to + 85°C
10
C
1
C
2
48
PARAMETER
Y0 Clock Capacitance
TYPICAL
8
15
UNITS
TEST CONDITIONS
V
CC
= 5.0V, V
PIN
= 2.0V
V
CC
= 5.0V, V
PIN
= 2.0V
Table 2-0006/1048E
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
pL
PARAMETER
SI
Data Retention Specifications
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Cycles
Table 2-0008/1048E
Data Retention
U
SE
is
Erase/Reprogram Cycles
3
S
Specifications
ispLSI 1048E
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
≤
3 ns 10% to 90%
1.5V
1.5V
See Figure 2
Table 2-0003/1048E
Figure 2. Test Load
+ 5V
R1
Device
Output
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
EW
*
CL includes Test Fixture and Probe Capacitance.
0213a
Table 2-0004a
Over Recommended Operating Conditions
10
48
DC Electrical Characteristics
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
EA
FO
C
R
N
CONDITION
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
SE
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
D
ES
IG
R2
CL
*
MIN.
–
2.4
–
–
–
–
–
–
TYP.
–
–
–
–
–
–
–
175
3
MAX. UNITS
0.4
–
-10
10
-150
-150
-200
–
V
V
μA
μA
μA
μA
mA
mA
Input or I/O High Leakage Current 3.5V
≤
V
IN
≤
V
CC
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
is
ispEN Input Low Leakage Current 0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V Commercial
I
CC
2, 4
1.
2.
3.
4.
–
175
–
mA
Industrial
f
CLOCK
= 1 MHz
One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test problems
Table 2-0007/1048E
by tester ground degradation. Characterized but not 100% tested.
Measured using twelve 16-bit counters.
Typical values are at V
CC
= 5V and T
A
= 25°C.
Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
U
pL
Input or I/O Low Leakage Current
SI
4
N
S
Test
Point
Specifications
ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
COND.
4
#
2
DESCRIPTION
1
-125
–
–
125.0
1
-100
–
–
100.0
71.0
6.5
–
125.0
10.0
12.5
–
–
–
–
–
–
-90
10.0
12.5
–
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
7.5
10.0
–
–
–
–
4.5
–
–
–
–
12.0
12.0
7.0
7.0
–
–
–
–
5.5
UNITS
ns
10
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
t
su3
t
h3
1.
2.
3.
4.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
–
–
1
2
3
4
5
6
7
8
9
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency, Max. Toggle
N
–
6.5
–
–
7.5
–
13.5
–
15.0
15.0
9.0
9.0
–
–
–
–
Clock Frequency with External Feedback
(
tsu2 + tco1
)
91.0
D
ES
IG
71.0
6.5
–
125.0
6.5
–
–
7.5
–
13.5
–
15.0
15.0
9.0
9.0
–
–
–
–
0.0
7.5
–
0.0
–
6.5
–
–
–
–
4.0
4.0
3.5
0.0
0.0
7.5
–
0.0
–
6.5
–
–
–
–
4.0
4.0
4.0
0.0
90.9
(
1
twh + twl
)
167.0
5.5
–
0.0
6.5
–
–
–
–
–
–
3.0
3.0
0.0
5.0
GLB Reg. Setup Time before Clock,4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
EW
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
N
10.0
R
FO
18 External Synchronous Clock Pulse Duration, High
20
21
EA
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0
48
19 External Synchronous Clock Pulse Duration, Low
U
SE
is
pL
SI
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
Table 2-0030A/1048E
5
S
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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