Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08QA4
Rev. 3, 1/2009
MC9S08QA4
8-Pin DFN
Case 1452-02
8-Pin NB-SOIC
Case 751-07
MC9S08QA4 Series
Covers:
MC9S08QA4
MC9S08QA2
Features:
• 8-bit HCS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature
range of –40°C to 85°C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Flash read/program/erase over full operating voltage
and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Two very low power stop modes
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Very low power real time counter for use in run, wait,
and stop modes with internal clock sources
• Clock Source Options
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports bus
frequencies from 1 MHz to 10 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1 kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt
– Selectable trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
8-Pin PDIP
Case 626-06
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• Peripherals
– ADC — 4-channel, 10-bit resolution; 1.7 mV/°C
temperature sensor; automatic compare function;
internal bandgap reference channel; operation in stop3;
fully functional from 3.6 V to 1.8 V
– ACMP — Analog comparator with selectable interrupt
on rising, falling, or either edge of comparator output;
compare option to fixed internal bandgap reference
voltage; output can be tied internally to TPM input
capture
– TPM — One 1-channel timer/pulse-width modulator
(TPM) module; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on
each channel; ACMP output can be tied internally to
input capture
– MTIM — 8-bit modulo timer module with 8-bit
prescaler
– KBI — 4-pin keyboard interrupt module with software
selectable polarity on edge or edge/level modes
• Input/Output
– Four GPIOs, one input-only pin and one output-only
pin.
– Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins except PTA5
• Package Options
– 8-pin SOIC, PDIP, and DFN
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2009. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .5
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .5
3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .6
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .10
3.7 Internal Clock Source (ICS) Characteristics . . . . . . . . .11
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . .
3.9 Analog Comparator (ACMP) Electricals . . . . . . . . . . .
3.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
12
13
14
15
15
17
19
19
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
1
2
3
Date
1/2008
2/2008
1/2009
Initial public release
Description of Changes
Changed the designator of the device in
Table 15.
Changed the condition of Run supply current measured to f
Bus
= 1 MHz in
Table 7.
Fixed the error of inconsistent table number.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08QA4RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08QA4 Series MCU Data Sheet, Rev. 3
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
BKGD/MS
IRQ
HCS08 CORE
DEBUG MODULE (DBG)
CPU
BDC
8-BIT MODULO TIMER
MODULE (MTIM)
PORT A
TCLK
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/ADP3
PTA2/KBIP2/ADP2
The block diagram,
Figure 1,
shows the structure of the MC9S08QA4 MCU.
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
IRQ
COP
LVD
4
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
ACMPO
ACMP–
ACMP+
4
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
16-BIT TIMER/PWM
MODULE (TPM)
TPMCH0
USER FLASH
(MC9S08QA4 = 4096 BYTES)
(MC9S08QA2 = 2048 BYTES)
ANALOG COMPARATOR
(ACMP)
PTA1/KBIP1/ADP1/ACMP–
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
USER RAM
(MC9S08QA4 = 256 BYTES)
(MC9S08QA2 = 160BYTES)
16 MHz INTERNAL CLOCK
SOURCE (ICS)
V
SS
V
DD
VOLTAGE REGULATOR
V
DDA
V
SSA
V
REFH
V
REFL
NOTES:
1
Port pins are software configurable with pullup device if input port.
2
Port pins are software configurable for output drive strength.
3
Port pins are software configurable for output slew rate control.
4
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
5
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
6
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
7
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can
be used to reconfigure the pullup as a pulldown device.
Figure 1. MC9S08QA4 Series Block Diagram
2
Pin Assignments
This section shows the pin assignments in the packages available for the MC9S08QA4 series.
MC9S08QA4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
3
Pin Assignments
Table 1. Pin Sharing Priority
Priority
PIN
Lowest
Port Pin
PTA5
1
PTA4
Alt 1
IRQ
Alt 2
TCLK
ACMPO
BKGD
Alt 3
Highest
Alt 4
RESET
MS
V
DD
V
SS
8-Pin
1
2
3
4
5
6
7
8
1
PTA3
PTA2
PTA1
PTA0
KBIP3
KBIP2
KBIP1
KBIP0
ADP3
ADP2
ADP1
2
TPMCH0
ADP0
2
ACMP–
2
ACMP+
2
2
Pin does not contain a clamp diode to V
DD
and must not be driven
above V
DD
. The voltage measured on the internally pulled-up RESET
pin will not be pulled to V
DD
. The internal gates connected to this pin
are pulled to V
DD
.
If ACMP and ADC are both enabled, both will have access to the pin.
PTA5/IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
V
DD
V
SS
1
2
3
4
8
7
6
5
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA1/KBIP1/ADP1/ACMP–
PTA2/KBIP2/ADP2
PTA3/KBIP3/ADP3
8-Pin PDIP/SOIC
PTA5/IRQ/TCLK/RESET
1
PTA4/ACMPO/BKGD/MS
2
V
DD
3
V
SS
4
8-Pin DFN
8
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
7
PTA1/KBIP1/ADP1/ACMP–
6
PTA2/KBIP2/ADP2
5
PTA3/KBIP3/ADP3
Figure 2. MC9S08QA4 Series in 8-Pin Packages
MC9S08QA4 Series MCU Data Sheet, Rev. 3
4
Freescale Semiconductor
Electrical Characteristics
3
3.1
Electrical Characteristics
Introduction
This chapter contains electrical and timing specifications for the MC9S08QA4 series of microcontrollers available at the time
of publication.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in
Table 2
may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V
SS
or V
DD
) or the programmable pullup resistor associated with the pin is enabled.
Table 2. Absolute Maximum Ratings
Rating
Supply voltage
Maximum current into V
DD
Digital input voltage
Instantaneous maximum current
Single pin limit (applies to all port pins)
1, 2, 3
Storage temperature range
1
Symbol
V
DD
I
DD
V
In
I
D
T
stg
Value
–0.3 to 3.8
120
–0.3 to V
DD
+ 0.3
±25
–55 to 150
Unit
V
mA
V
mA
°C
2
3
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (V
DD
) and negative (V
SS
) clamp
voltages, then use the larger of the two resistance values.
All functional non-supply pins are internally clamped to V
SS
and V
DD
.
Power supply must maintain regulation within operating V
DD
range during instantaneous and
operating maximum current conditions. If positive injection current (V
In
> V
DD
) is greater than
I
DD
, the injection current may flow out of V
DD
and could result in external power supply going
out of regulation. Ensure external V
DD
load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P
I/O
into account in power calculations, determine
the difference between actual pin voltage and V
SS
or V
DD
and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and V
SS
or V
DD
will be very small.
MC9S08QA4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
5
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