Da ta S h e e t , V 3 .0 , J a n . 2 00 1
C161CS-32R/-L
C161JC-32R/-L
C161JI-32R/-L
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2001-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
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approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
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Da ta S h e e t , V 3 .0 , J a n . 2 00 1
C161CS-32R/-L
C161JC-32R/-L
C161JI-32R/-L
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C161CS/JC/JI
Revision History:
Previous Version:
Page
All
2
27, 28
29
35
39ff
51
53
57
60
62
63
65ff
1)
2001-01
2000-08 V2.0 (intermediate version)
1999-03
(Advance Information)
V3.0
Subjects (major changes since last revision)
1)
Converted to Infineon layout
Derivative Synopsis Table updated
GPT block diagrams updated
RTC description improved
OWD description improved
RSTCON and SDLM registers added
Description of input/output voltage and hysteresis improved
Separate table for power consumption
Clock generation mode table updated
External clock drive specification improved
Reset calibration time specified, definition of
V
AREF
improved
Programmable sample time introduced
Timing tables updated to 25 MHz
4, 6, 10, 18
Programmable Interface Routing introduced
Changes refer to version 1999-03.
Controller Area Network (CAN): License of Robert Bosch GmbH
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Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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16-Bit Single-Chip Microcontroller
C166 Family
C161CS/JC/JI
C161CS/JC/JI
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16
×
16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 59 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
– Additional 32 kHz Oscillator
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
– 8 KBytes On-Chip Extension RAM (XRAM)
– 256 KBytes On-Chip Mask ROM
• On-Chip Peripheral Modules
– 12-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8
µs
– Two 16-Channel Capture/Compare Units (eight IO lines each)
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Asynchronous/Synchronous Serial Channels
– High-Speed Synchronous Serial Channel (SPI)
– On-Chip CAN Interface (Rev. 2.0B active, Full CAN / Basic CAN)
with 15 Message Objects (C161CS
2x, C161JC 1x)
– Serial Data Link Module (SDLM), compliant with J1850,
supporting Class 2 (C161JC/JI)
– IIC Bus Interface (10-bit Addressing, 400 kHz) with 2 Channels (multiplexed)
– On-Chip Real Time Clock
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
Data Sheet
1
V3.0, 2001-01
模拟与混合信号
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