56F8365/56F8165
Data Sheet
Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8365
Rev. 9
02/2012
freescale.com
Document Revision History
Version History
Rev 0
Rev 1.0
Rev 2.0
Pre-release, Alpha customers only
Initial Public Release
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall life
expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed P
D
in
Table 10-3.
Corrected note about average value for Flash Data Retention in
Table 10-4.
Added new RoHS-compliant orderable part numbers in
Table 13-1.
Corrected Data Flash on page 5
Deleted RSTO from Pin Group 2 (listed after
Table 10-1).
Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Added information/corrected state during reset in
Table 2-2.
Clarified external reference crystal
frequency for PLL in
Table 10-14
by increasing maximum value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a debugging
environment, TRST may be tied to V
SS
through a 1K resistor.
Rev. 8
• Remove pullup comment from PWM pins in
Table 2-2.
• Add
Figure 10-1
showing current voltage characteristics.
• In
Table 10-23,
correct interpretation of Calibration Factors to be viewed as worst case
factors.
• Add to
Table 10-23
the DC drift of ADC over temperature.
Rev 8.1
• Removed “Preliminary” markings.
Description of Change
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev. 7
Please see http://www.freescale.com for the most current data sheet revision.
56F8365 Technical Data, Rev. 9
2
Freescale Semiconductor
Table of Contents
Part 1: Overview 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
56F8365/56F8165 Features 5
Device Description 8
Award-Winning Development Environment 10
Architecture Block Diagram 10
Product Documentation 13
Data Sheet Conventions 14
Part 8: General Purpose Input/Output (GPIO)
133
8.1. Introduction 133
8.2. Memory Maps 133
8.3. Configuration 133
Part 9: Joint Test Action Group (JTAG) 138
9.1. JTAG Information 138
Part 2: Signal/Connection Descriptions 14
2.1. Introduction 14
2.2. Signal Pins 18
Part 10: Specifications 138
10.1. General Characteristics 138
10.2. DC Electrical Characteristics 143
10.3. AC Electrical Characteristics 148
10.4. Flash Memory Characteristics 148
10.5. External Clock Operation Timing 149
10.6. Phase Locked Loop Timing 149
10.7. Crystal Oscillator Timing 150
10.8. Reset, Stop, Wait, Mode Select, and Interrupt
Timing 150
10.9. Serial Peripheral Interface (SPI) Timing 153
10.10. Quad Timer Timing 157
10.11. Quadrature Decoder Timing 157
10.12. Serial Communication Interface (SCI) Timing 158
10.13. Controller Area Network (CAN) Timing 159
10.14. JTAG Timing 159
10.15. Analog-to-Digital Converter (ADC) Parameters
161
10.16. Equivalent Circuit for ADC Inputs 163
10.17. Power Consumption 164
Part 3: On-Chip Clock Synthesis (OCCS) 36
3.1. Introduction 36
3.2. External Clock Operation 36
3.3. Registers 38
Part 4: Memory Map 38
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction 38
Program Map 39
Interrupt Vector Table 41
Data Map 44
Flash Memory Map 45
EOnCE Memory Map 46
Peripheral Memory Mapped Registers 47
Factory Programmed Memory 79
Part 5: Interrupt Controller (ITCN) 79
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction 79
Features 79
Functional Description 80
Block Diagram 81
Operating Modes 81
Register Descriptions 82
Resets 109
Part 11: Packaging 166
11.1. 56F8365 Package and Pin-Out Information 166
11.2. 56F8165 Package and Pin-Out Information 169
Part 12: Design Considerations 174
12.1. Thermal Design Considerations 174
12.2. Electrical Design Considerations 175
12.3. Power Distribution and I/O Ring Implementation
176
Part 6: System Integration Module (SIM) 110
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Introduction 110
Features 110
Operating Modes 111
Operating Mode Register 111
Register Descriptions 112
Clock Generation Overview 127
Power-Down Modes Overview 127
Stop and Wait Mode Disable Function 128
Resets 128
Part 13: Ordering Information 178
Part 7: Security Features 129
7.1. Operation with Security Enabled 129
7.2. Flash Access Blocking Mechanisms 129
56F8365 Technical Data, Rev. 9
Freescale Semiconductor
3
56F8365/56F8165 General Description
Note:
Features in italics are NOT available in the 56F8165 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 512KB Program Flash
• 4KB Program RAM
• 32KB Data Flash
• 32KB Data RAM
• 32KB Boot Flash
•
Up to two
6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
•
Up to two
Quadrature Decoders
• Up to two FlexCAN modules
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
56F8365 Technical Data, Rev. 9
4
Freescale Semiconductor
56F8365/56F8165 Features
RSTO
RESET
6
PWM Outputs
3
4
Current Sense Inputs
or
GPIOC
Fault Inputs
Program Controller
and Hardware
Looping Unit
5
JTAG/
EOnCE
Port
V
PP
2
V
CAP
4
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
V
DDA
2
V
SSA
PWMA
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
6
PWM Outputs
3
4
4
4
5
4
4
Current Sense Inputs
or GPIOD
Fault Inputs
PWMB
Address
Generation
Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
AD0
AD1
PAB
PDB
CDBR
CDBW
ADCA
Memory
Program Memory
256K x 16 Flash
2K x 16 RAM
Boot ROM
16K x 16 Flash
Data Memory
16K x 16 Flash
16K x 16 RAM
R/W Control
VREF
AD0
ADCB
AD1
Temp_Sense
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
External Bus
Interface Unit
*
External
Address Bus
Switch
*
External
Data
Bus Switch
*
Bus
Control
6
5
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
D7-10 or GPIOF0-3
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC
Quad Timer
C or GPIOE
Quad Timer
D or
GPIOE
FlexCAN
System Bus
Control
4
4
GPIOD2-5 or CS4-7
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
2
4
2
Decoding
Peripherals
RW
Control
IPAB
IPWDB
IPRDB
GPIO
or
EMI CS or
FlexCAN2
GPIOD0 (CS2 or
CAN2_TX)
GPIOD1 (CS3 or
CAN2_RX)
*
EMI not functional in
this package; use as
GPIO pins
Clock
resets
PLL
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
Interrupt
COP/
Watchdog Controller
System
P
Integration
O
R
Module
CLKO
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA IRQB
CLKMODE
56F8365/56F8165 Block Diagram
Part 1 Overview
1.1 56F8365/56F8165 Features
1.1.1
•
•
•
•
•
•
•
•
Core
Efficient 16-bit 56800E family controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
56F8365 Technical Data, Rev. 9
Freescale Semiconductor
5
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