Preliminary
Information
DUAL UART WITH 128-byte FIFOs AND
RS-485 HALF DUPLEX CONTROL
XR16C2850
DESCRIPTION
The XR16C2850 (2850) is a dual universal asynchronous receiver and transmitter (UART). The 2850 provides
enhanced UART functions with 128 byte FIFO, automatic RS-485 half duplex control, a modem control interface,
and data rates up to 1.5 Mbps. Onboard status registers provide the user with error indications and operational
status. System interrupts and modem control features may be tailored by external software to meet specific user
requirements. An internal loopback capability allows onboard diagnostics. Independent programmable baud rate
generators are provided to select transmit and receive clock rates up to 1.5 Mbps. The baud rate generator can
be configured for either crystal or external clock input. The 2850 is available in a 40-pin PDIP, 44-pin PLCC, and
48-pin TQFP packages. The 40 pin package does not offer TXRDY and RXRDY pins (DMA Signal monitoring).
Otherwise the three package versions are the same. The 2850 is functionally compatible with the ST16C2550.
The 2850 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.
FEATURES
•
Pin and functionally compatible to ST16C2550,
software compatible with INS8250, NS16C550
•
1.5 Mbps transmit/receive operation (24 MHz
Max.).
•
128 byte transmit FIFO to reduce bandwidth re-
quirement of the external CPU.
•
128 byte receive FIFO with error flags to reduce
bandwidth requirement of the external CPU.
•
Independent transmit and receive UART control.
•
RS-485 half duplex control.
•
Programmable transmit/receive FIFO trigger lev-
els.
•
Hardware / software flow control.
•
Selectable RTS flow control hysterisis.
•
Modem control signals (-CTS, -RTS, -DSR, -DTR,
-RI, -CD, and software controllable line break).
•
Programmable character lengths (5, 6, 7, 8) with
even, odd, or no parity.
•
Infrared receive and transmit encoder/decoder.
•
Device identification.
•
Crystal or external clock input.
•
460.8 Kbps transmit/receive operation with 7.3728
MHz crystal or external clock source.
PLCC Package
-TXRDYA
-DSRA
41
-CTSA
40
-CDA
42
VCC
44
D5
D6
D7
RXB
RXA
-TXRDYB
TXA
TXB
-OPB
-CSA
-CSB
7
8
9
10
11
12
13
14
15
16
17
XTAL1 18
XTAL2 19
-IOW 20
-CDB 21
GND 22
-RXRDYB 23
-IOR 24
-DSRB 25
-RIB 26
-RTSB 27
-CTSB 28
43
6
5
4
3
2
1
-RIA
D4
D3
D2
D1
D0
39
38
37
36
35
RESET
-DTRB
-DTRA
-RTSA
-OPA
-RXRDYA
INTA
INTB
A0
A1
A2
XR16C2850CJ
34
33
32
31
30
29
ORDERING INFORMATION
Part number
XR16C2850CP
XR16C2850CJ
XR16C2850CM
40
44
48
Pins Package
PDIP
PLCC
TQFP
Operating temperature
0° C to + 70° C
0° C to + 70° C
0° C to + 70° C
Part number
XR16C2850IP
XR16C2850IJ
XR16C2850IM
40
44
48
Pins Package
PDIP
PLCC
TQFP
Operating temperature
-40° C to + 85° C
-40° C to + 85° C
-40° C to + 85° C
Rev. 1.00P
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
XR16C2850
Figure 1, Package Descriptions, 40 pin, 48 pin XR16C2850
48 Pin TQFP Package
40 Pin DIP Package
-RSCTL
-DSRA
-CTSA
-CDA
VCC
N.C.
-RIA
D4
D3
D2
D1
D0
D0
D1
36
35
34
33
32
RESET
-DTRB
-DTRA
-RTSA
-OPA
N.C.
INTA
INTB
A0
A1
A2
N.C.
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
VCC
-RIA
-CDA
-DSRA
-CTSA
RESET
-DTRB
-DTRA
-RTSA
-OPA
INTA
INTB
A0
A1
A2
-CTSB
-RTSB
-RIB
-DSRB
-IOR
48
47
46
45
44
43
42
41
40
39
38
37
D5
D6
D7
RXB
RXA
N.C.
TXA
TXB
-OPB
-CSA
-CSB
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D2
D3
D4
D5
D6
D7
RXB
RXA
TXA
TXB
-OPB
-CSA
-CSB
XTAL1
XTAL2
-IOW
-CDB
GND
XR16C2850CM
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
17
18
19
20
XR16C2850CP
32
31
30
29
28
27
26
25
24
23
22
21
XTAL1
XTAL2
-DSRB
-IOW
GND
-IOR
N.C.
-RTSB
Rev. 1.00P
2
-CTSB
-CDB
N.C.
-RIB
XR16C2850
Figure 2, Block Diagram
D0-D7
-IOR
-IOW
RESET
Data bus
&
Control Logic
Transmit
FIFO
Registers
Transmit
Shift
Register
TX A/B
TXIR A/B
Flow
Control
Logic
Inter Connect Bus Lines
&
Control signals
Receive
FIFO
Registers
Ir
Encoder
Receive
Shift
Register
A0-A2
-CS A/B
-RSCTL
Register
Select
Logic
RX A/B
RXIR A/B
INT A/B
-RXRDY A/B
-TXRDY A/B
Interrupt
Control
Logic
Flow
Control
Logic
Ir
Decoder
-DTR A/B
-RTS A/B
Clock
&
Baud Rate
Generator
XTAL1
XTAL2
Modem
Control
Logic
-CTS A/B
-RI A/B
-CD A/B
-DSR A/B
Rev. 1.00P
3
XR16C2850
SYMBOL DESCRIPTION
Symbol
A0
A1
A2
-CS A-B
40
28
27
26
14,15
Pin
44
31
30
29
16,17
48
28
27
26
10,11
Signal
type
I
I
I
I
Pin Description
Address-0 Select Bit. - Internal register address selection.
Address-1 Select Bit. - Internal register address selection.
Address-2 Select Bit. - Internal register address selection.
Chip Select A, B (active low) - This function is associated
with individual channels, A through B. These pins enable
data transfers between the user CPU and the 2850 for the
channel(s) addressed. Individual UART sections (A, B) are
addressed by providing a logic 0 on the respective -CS A-
B pin.
Data Bus (Bi-directional) - These pins are the eight bit, three
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
Signal and power ground.
Interrupt A, B (three state) - This function is associated with
individual channel interrupts, INT A-B. INT A-B are enabled
when MCR bit-3 is set to a logic 1, interrupts are enabled in
the interrupt enable register (IER), and when an interrupt
condition exists. Interrupt conditions include: receiver er-
rors, available receiver buffer data, transmit buffer empty,
or when a modem status flag is detected.
Read strobe (active low strobe) - A logic 0 transition on this
pin will load the contents of an Internal register defined by
address bits A0-A2 onto the 2850 data bus (D0-D7) for
access by an external CPU.
Write strobe (active low strobe) - A logic 0 transition on this
pin will transfer the contents of the data bus (D0-D7) from
the external CPU to an internal register that is defined by
address bits A0-A2.
D0-D7
1-8
2-9
44-48
1-3
I/O
GND
INT A-B
20
30,29
22
33,32
17
30,29
Pwr
O
-IOR
21
24
19
I
-IOW
18
20
15
I
Rev. 1.00P
4
XR16C2850
SYMBOL DESCRIPTION
Symbol
-OP2 A-B
40
31,13
Pin
44
35,15
48
32,9
Signal
type
O
Pin Description
Output -2 (User Defined) - This function is associated with
individual channels, A through B. The state at these pin(s)
are defined by the user and through the software setting of
MCR register bit-3. INT A-B are set to the active mode and
OP2 to a logic 0 when MCR-3 is set to a logic 1. INT A-B are
set to the three state mode and OP2 to a logic 1 when MCR-
3 is set to a logic 0. See bit-3, Modem Control Register
(MCR bit-3).
Reset (active high) - A logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time (see XR16C2850 External Reset Conditions for initial-
ization details).
Receive Ready A-B (active low) - This function is associ-
ated with 44 pin PLCC and 48 pin TQFP packages only. This
function provides the RX FIFO/RHR status for individual
receive channels (A-B). RXRDY is primarily intended for
monitoring DMA mode 1 transfers for the receive data
FIFOs. A logic 0 indicates there is receive data to read/
unload, i.e., receive ready status with one or more RX
characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed
trigger level has not been reached. This signal can also be
used for single mode transfers (DMA mode 0).
Transmit Ready A-B (active low) - This function is associ-
ated with 44 pin PLCC and 48 pin TQFP packages only.
These outputs provide the TX FIFO/THR status for indi-
vidual transmit channels (A-B). TXRDY is primarily in-
tended for monitoring DMA mode 1 transfers for the trans-
mit data FIFOs. An individual channels -TXRDY A-B buffer
ready status is indicated by logic 0, i.e., at least one location
is empty and available in the FIFO or THR. This pin goes to
a logic 1 when there are no more empty locations in the
FIFO or THR. This signal can also be used for single mode
transfers (DMA mode 0).
Power supply input.
RESET
35
39
36
I
-RXRDY A-B
-
34,23
31,18
O
-TXRDY A-B
-
1,12
43,6
O
VCC
Rev. 1.00P
40
44
42
Pwr
5
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