Document Revision History
Version History
Rev. 0
Rev. 1
Initial public release.
• In Table 10-4, added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby
mode from 400kHz to 200kHz.
• Changed input propagation delay values in Table 10-20 as follows:
Old values: 1
μs
typical, 2
μs
maximum
New values: 35 ns typical, 45 ns maximum
Rev. 2
In Table 10-19, changed the maximum ADC internal clock frequency from 8 MHz to 5.33
MHz.
• Added the following note to the description of the TMS signal in Table 2-3:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
Old labels: Pin 1, Pin 12, Pin 23, Pin 34
New labels: Pin 1, Pin 9, Pin 17, Pin 25
Rev. 4
• Changed the ITCN_BASE address In
Table 5-3
(was $00 F060, is $00 F0E0).
• Changed the VBA register reset value and updated the footnote in
Section 5.6.8.
• Changed the STANDBY > STOP I
DD
values in
Table 10-6
as follows:
Typical: was 290μA, is 540μA
Maximum: was 390μA, is 650μA
• Changed the POWERDOWN I
DD
values in
Table 10-6
as follows:
Typical: was 190μA, is 440μA
Maximum: was 250μA, is 550μA
• Changed footnote 1 in
Table 10-12
(was “Output frequency after application of 8MHz
trim value, at 125°C.”, is “Output frequency after application of factory trim”).
• Deleted the text “at 125°C” from
Figure 10-5.
• Changed the maximum input offset voltage in
Table 10-20
(was +/- 20 mV, is ±35 mV).
Rev. 5
• Revised
Section 7, Security Features.
• Fixed miscellaneous typos.
• Corrected pin number labels in Figure 11-1 as follows:
Description of Change
Rev. 3
56F8033/56F8023 Data Sheet, Rev. 6
2
Freescale Semiconductor
56F8033/56F8023 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 56F8033 offers 64KB (32K x 16) Program Flash
• 56F8023 offers 32KB (16K x 16) Program Flash
• 56F8033 offers 8KB (4K x 16) Unified Data/Program
RAM
• 56F8023 offers 4KB (2K x 16) Unified Data/Program
RAM
• One 6-channel PWM module
• Two 3-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two Internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
RESET or
GPIOA
• One Programmable Interval Timer (PIT)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I
2
C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
V
CAP
4
JTAG/EOnCE
Port or
GPIOD
V
DD
V
SS
2
V
DDA
V
SSA
Digital Reg
5
Analog Reg
PWM
or TMRA or GPIOA
Program Controller
and Hardware
Looping Unit
16-Bit
56800E Core
Low-Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
DAC
4
PAB
PDB
CDBR
CDBW
AD0
ADC
or CMP
or GPIOC
Memory
Program Memory
16K x 16 Flash
32K x 16 Flash
Unified Data /
Program RAM
2K x 16
4K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
4
AD1
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I
2
C
or CMP
or GPIOB
QSPI
or PWM
or I
2
C
or TMRA
or GPIOB
4
QSCI
or PWM
or I
2
C
or TMRA
or GPIOB
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
O
Clock
S
Generator*
C
2
2
*Includes On-Chip
Relaxation Oscillator
56F8033/56F8023 Block Diagram
56F8033/56F8023 Data Sheet, Rev. 6
4
Freescale Semiconductor
56F8033/56F8023 Data Sheet Table of Contents
Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
1.4
1.5
1.6
56F8033/56F8023 Features . . . . . . . . . . . 6
56F8033/56F8023 Description . . . . . . . . . 8
Award-Winning Development
Environment . . . . . . . . . . . . . . . . . . . 9
Architecture Block Diagram . . . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . 17
Data Sheet Conventions . . . . . . . . . . . . . 17
7.3
Product Analysis. . . . . . . . . . . . . . . . . . 109
Part 8 General-Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .109
8.1
8.2
8.3
Introduction. . . . . . . . . . . . . . . . . . . . . . 109
Configuration . . . . . . . . . . . . . . . . . . . . 109
Reset Values . . . . . . . . . . . . . . . . . . . . 111
Part 9 Joint Test Action Group (JTAG) . . .117
Part 2 Signal/Connection Descriptions . . . 18
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . 18
56F8033/56F8023 Signal Pins . . . . . . . . 22
9.1
56F8033/56F8023 Information . . . . . . . 117
Part 10Specifications. . . . . . . . . . . . . . . . . .117
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
General Characteristics . . . . . . . . . . . . 117
DC Electrical Characteristics . . . . . . . . 121
AC Electrical Characteristics . . . . . . . . 124
Flash Memory Characteristics . . . . . . . 125
External Clock Operation Timing . . . . . 125
Phase Locked Loop Timing . . . . . . . . . 126
Relaxation Oscillator Timing. . . . . . . . . 126
Reset, Stop, Wait, Mode Select, and Interrupt
Timing . . . . . . . . . . . . . . . . . . . . . 128
Serial Peripheral Interface (SPI) Timing 129
Quad Timer Timing. . . . . . . . . . . . . . . . 133
Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . 134
Inter-Integrated Circuit Interface (I2C)
Timing . . . . . . . . . . . . . . . . . . . . . 135
JTAG Timing. . . . . . . . . . . . . . . . . . . . . 136
Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 138
Equivalent Circuit for ADC Inputs . . . . . 139
Comparator (CMP) Parameters . . . . . . 140
Digital-to-Analog Converter (DAC)
Parameters . . . . . . . . . . . . . . . . . 140
Power Consumption . . . . . . . . . . . . . . . 142
Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . 31
Features . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating Modes . . . . . . . . . . . . . . . . . . 31
Internal Clock Source . . . . . . . . . . . . . . . 32
Crystal Oscillator. . . . . . . . . . . . . . . . . . . 32
Ceramic Resonator . . . . . . . . . . . . . . . . . 33
External Clock Input - Crystal Oscillator
Option. . . . . . . . . . . . . . . . . . . . . . . 33
Alternate External Clock Input . . . . . . . . 34
Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 34
4.1
4.2
4.3
4.4
4.5
4.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . 34
Interrupt Vector Table . . . . . . . . . . . . . . . 35
Program Map . . . . . . . . . . . . . . . . . . . . . 37
Data Map . . . . . . . . . . . . . . . . . . . . . . . . 37
EOnCE Memory Map . . . . . . . . . . . . . . . 39
Peripheral Memory-Mapped Registers . . 40
Part 5 Interrupt Controller (ITCN) . . . . . . . . 54
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . 54
Features . . . . . . . . . . . . . . . . . . . . . . . . . 54
Functional Description . . . . . . . . . . . . . . 55
Block Diagram. . . . . . . . . . . . . . . . . . . . . 57
Operating Modes . . . . . . . . . . . . . . . . . . 57
Register Descriptions . . . . . . . . . . . . . . . 57
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Part 11Packaging . . . . . . . . . . . . . . . . . . . . .144
11.1
56F8033/56F8023 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 144
Part 12Design Considerations . . . . . . . . . .148
Part 6 System Integration Module (SIM) . . . 77
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . 77
Features . . . . . . . . . . . . . . . . . . . . . . . . . 77
Register Descriptions . . . . . . . . . . . . . . . 78
Clock Generation Overview . . . . . . . . . 102
Power-Saving Modes . . . . . . . . . . . . . . 103
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 104
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 107
12.1
12.2
Thermal Design Considerations . . . . . . 148
Electrical Design Considerations . . . . . 149
Part 13Ordering Information . . . . . . . . . . . .150
Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .151
Part 7 Security Features. . . . . . . . . . . . . . . 107
7.1
7.2
Operation with Security Enabled. . . . . . 107
Flash Access Lock and Unlock
Mechanisms . . . . . . . . . . . . . . . . . 108
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
5
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