SiM3U1xx/SiM3C1xx
SiM3U1
XX
/SiM3C1
XX
R
EFERENCE
M
ANUAL
This reference manual accompanies several documents to provide the complete description of SiM3U1xx/
SiM3C1xx devices, part of the Silicon Laboratories 32-bit ARM Cortex-M3 family of microcontrollers.
This document provides the detailed description for all peripherals available on all SiM3U1xx/SiM3C1xx devices.
The peripheral mix varies across different members of the device families. Refer to the device data sheet for details
on the specific peripherals available for each member of the device family. In the event that the device data sheet
and this document contain conflicting information, the device data sheet should be considered the authoritative
source.
Watchdog
Timer
(WDTIMER0)
Power On Reset /
PMU
Debug /
Programming
Hardware
Analog
Core
ARM Cortex M3
AHB
APB
SARADC0
IDAC0
SARADC1
IDAC1
Comparator 0 Comparator 1
Memory
IVC0
Capacitive Sensing 0
Voltage Supply
Monitor (VMON0)
32/64/128/256 kB Flash
4/12/28 kB RAM
Power
Low Dropout Regulator (LDO0)
Voltage Regulator (VREG0)
External Regulator (EXTVREG0)
Power Management Unit (PMU)
I/O
4 kB retention RAM
USB0
DMA
16-Channel Controller
Peripheral Crossbar
2 kB Buffer
5 Bidirectional
Endpoints
Internal Oscillator
EMIF
Crossbars
Standard I/O pins
5 V tolerant pins
High Drive pins
Clocking
Digital
Real-Time Clock (RTC0OSC)
USART0
USART1
UART0
UART1
Low Frequency Oscillator (LFOSC0)
SPI0
Low Power Oscillator (LPOSC0)
USB Oscillator (USB0OSC)
External Oscillator Control (EXTOSC0)
EPCA0
Phase-Locked Loop (PLL0OSC)
AES0
Peripheral Clock Control (CLKCTRL)
CRC0
Timer 0
Timer 1
PCA0
PCA1
Clock Control
I2C0
I2S0
I2C1
SPI1
SPI2
Low Power Timer (LPTIMER0)
DMA access available for these peripherals
Rev. 1.0 11/12
Copyright © 2012 by Silicon Laboratories
SiM3U1xx/SiM3C1xx
SiM3U1xx/SiM3C1xx
Ta ble of Contents
1. Related Documents and Conventions ............................................................................. 11
1.1. Related Documents...................................................................................................... 11
1.2. Conventions ................................................................................................................. 11
2. Memory Organization ........................................................................................................12
2.1. Flash Region ................................................................................................................ 13
2.2. RAM Region ................................................................................................................. 14
2.3. Peripheral Region......................................................................................................... 15
2.4. External Memory .......................................................................................................... 16
2.5. Cortex-M3 Internal Peripherals .................................................................................... 16
3. SiM3U1xx/SiM3C1xx Register Memory Map.................................................................... 17
4. Interrupts ............................................................................................................................ 34
4.1. System Exceptions....................................................................................................... 34
4.2. Interrupt Vector Table................................................................................................... 35
4.3. Priorities ....................................................................................................................... 40
5. Clock Control (CLKCTRL0) ............................................................................................... 43
5.1. Clock Control Features.................................................................................................43
5.2. CLKCTRL0 Registers................................................................................................... 45
5.3. CLKCTRL0 Register Memory Map............................................................................... 53
6. Reset Sources (RSTSRC0)................................................................................................ 55
6.1. Reset Sources Features............................................................................................... 55
6.2. RSTSRC0 Registers .................................................................................................... 59
6.3. RSTSRC0 Register Memory Map ................................................................................ 64
7. Register Security (LOCK0)................................................................................................ 65
7.1. Security Features ......................................................................................................... 65
7.2. LOCK0 Registers ......................................................................................................... 66
7.3. LOCK0 Register Memory Map ..................................................................................... 72
8. Port I/O Configuration ....................................................................................................... 73
8.1. Port Bank Description................................................................................................... 73
8.2. Crossbars ..................................................................................................................... 74
8.3. Port Bank Standard (PBSTD) Features ....................................................................... 85
8.4. Standard Modes of Operation ...................................................................................... 86
8.5. Assigning Standard Port Bank Pins to Analog and Digital Functions........................... 86
8.6. Standard Port Match and Capacitive Sensing (CAPSENSE0) Activity Monitoring ...... 87
8.7. Standard Port Bank Pulse Generator........................................................................... 87
8.8. High Drive (PBHD) Features ........................................................................................ 88
8.9. High Drive Modes of Operation .................................................................................... 89
8.10.High Drive Configuration Procedure ............................................................................90
8.11.High Drive Function Selection...................................................................................... 90
8.12.Port Bank Security ....................................................................................................... 92
8.13.Ports and Power Mode 9 ............................................................................................. 92
8.14.Debugging Interfaces................................................................................................... 93
8.15.External Memory Interface (EMIF)............................................................................... 94
8.16.External Interrupts........................................................................................................97
8.17.PBCFG0 Registers ...................................................................................................... 99
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SiM3U1xx/SiM3C1xx
8.18.PBCFG0 Register Memory Map ................................................................................ 112
8.19.PBSTD0, PBSTD1, PBSTD2, and PBSTD3 Registers..............................................114
8.20.PBSTDn Register Memory Map.................................................................................125
8.21.PBHD4 Registers....................................................................................................... 128
8.22.PBHD4 Register Memory Map................................................................................... 140
9. Power ................................................................................................................................ 142
9.1. Power Modes .............................................................................................................142
9.2. Power Management Unit (PMU0) .............................................................................. 144
9.3. PMU0 Registers ......................................................................................................... 147
9.4. PMU0 Register Memory Map ..................................................................................... 156
10. Core Voltage Regulator (LDO0) ...................................................................................... 158
10.1.Core Voltage Regulator Features .............................................................................. 158
10.2.Functional Description ...............................................................................................159
10.3.LDO0 Registers ......................................................................................................... 160
10.4.LDO0 Register Memory Map ..................................................................................... 161
11. Device Identification (DEVICEID0) and Universally Unique Identifier......................... 162
11.1.Device ID Features .................................................................................................... 162
11.2.Universally Unique Identifier (UUID) ..........................................................................162
11.3.DEVICEID0 Registers................................................................................................ 163
11.4.DEVICEID0 Register Memory Map............................................................................ 167
12. Advanced Encryption Standard (AES0)......................................................................... 169
12.1.AES Features.............................................................................................................169
12.2.Overview ....................................................................................................................170
12.3.Interrupts....................................................................................................................170
12.4.Debug Mode .............................................................................................................. 170
12.5.DMA Configuration and Usage .................................................................................. 171
12.6.Using the AES0 Module for Electronic Codebook (ECB)........................................... 173
12.7.Using the AES0 Module for Cipher Block Chaining (CBC) ........................................ 176
12.8.Using the AES0 Module for Counter (CTR) ............................................................... 183
12.9.Performing “In-Place” Ciphers ................................................................................... 186
12.10.Using the AES0 Module in Software Mode.............................................................. 187
12.11.AES0 Registers........................................................................................................ 188
12.12.AES0 Register Memory Map ................................................................................... 208
13. Capacitive Sensing (CAPSENSE0).................................................................................212
13.1.Capacitive Sensing Features ..................................................................................... 212
13.2.Overview ....................................................................................................................213
13.3.Measurement Overview ............................................................................................. 214
13.4.Conversion and Input Modes ..................................................................................... 216
13.5.Conversion Rate ........................................................................................................ 217
13.6.Accumulation Modes.................................................................................................. 217
13.7.Measuring Multiple Channels in a Single Measurement............................................ 217
13.8.Pin Monitoring ............................................................................................................217
13.9.Compare Threshold ................................................................................................... 218
13.10.Interrupts.................................................................................................................. 218
13.11.Additional Options.................................................................................................... 218
13.12.Taking a Measurement ............................................................................................ 219
Rev. 1.0
3
SiM3U1xx/SiM3C1xx
13.13.CAPSENSE0 Registers ........................................................................................... 220
13.14.CAPSENSE0 Register Memory Map ....................................................................... 230
14. Comparator (CMP0 and CMP1)....................................................................................... 232
14.1.Comparator Features................................................................................................. 232
14.2.Overview ....................................................................................................................233
14.3.Inputs ......................................................................................................................... 233
14.4.Outputs ...................................................................................................................... 239
14.5.Response Time.......................................................................................................... 240
14.6.Hysteresis .................................................................................................................. 240
14.7.Interrupts and Flags ................................................................................................... 240
14.8.CMP0 and CMP1 Registers....................................................................................... 241
14.9.CMPn Register Memory Map..................................................................................... 246
15. Cyclic Redundancy Check (CRC0).................................................................................247
15.1.CRC Features ............................................................................................................ 247
15.2.Overview ....................................................................................................................248
15.3.Interrupts....................................................................................................................248
15.4.DMA Configuration and Usage .................................................................................. 248
15.5.Byte-Level Bit Reversal and Byte Reordering............................................................249
15.6.CRC0 Registers ......................................................................................................... 252
15.7.CRC0 Register Memory Map..................................................................................... 256
16. DMA Controller (DMACTRL0) ......................................................................................... 257
16.1.DMA Controller Features ........................................................................................... 257
16.2.Overview ....................................................................................................................259
16.3.Interrupts....................................................................................................................259
16.4.Configuring a DMA Channel ...................................................................................... 259
16.5.DMA Channel Transfer Structures............................................................................. 260
16.6.Transfer Types........................................................................................................... 265
16.7.Data Requests ........................................................................................................... 272
16.8.Masking Channels ..................................................................................................... 273
16.9.Errors ......................................................................................................................... 273
16.10.Arbitration................................................................................................................. 274
16.11.DMACTRL0 Registers ............................................................................................. 275
16.12.DMACTRL0 Register Memory Map ......................................................................... 309
17. DMA Crossbar (DMAXBAR0) .......................................................................................... 314
17.1.DMA Crossbar Features ............................................................................................ 314
17.2.Channel Priority ......................................................................................................... 315
17.3.DMAXBAR0 Registers ...............................................................................................316
17.4.DMAXBAR0 Register Memory Map........................................................................... 323
18. External Memory Interface (EMIF0) ................................................................................ 324
18.1.EMIF Features ........................................................................................................... 324
18.2.Overview ....................................................................................................................325
18.3.Signal Descriptions .................................................................................................... 326
18.4.Memory Interface ....................................................................................................... 328
18.5.Non-Multiplexed Output Mode ................................................................................... 330
18.6.Multiplexed Output Mode ........................................................................................... 330
18.7.Mixing Configurations ................................................................................................ 331
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SiM3U1xx/SiM3C1xx
18.8.Transaction Timing .................................................................................................... 332
18.9.Idle and Off States ..................................................................................................... 334
18.10.Additional Features .................................................................................................. 334
18.11.Configuring the External Memory Interface ............................................................. 334
18.12.EMIF0 Registers ......................................................................................................335
18.13.EMIF0 Register Memory Map .................................................................................. 337
18.14.EMIF0_IFx Registers ...............................................................................................338
18.15.EMIFn_IFx Register Memory Map ........................................................................... 348
19. External Oscillator (EXTOSC0) ....................................................................................... 350
19.1.External Oscillator Features....................................................................................... 350
19.2.Introduction ................................................................................................................ 351
19.3.External Crystal Oscillator.......................................................................................... 351
19.4.External CMOS Oscillator .......................................................................................... 352
19.5.External RC Oscillator................................................................................................ 353
19.6.External C Oscillator .................................................................................................. 355
19.7.EXTOSC0 Registers .................................................................................................. 357
19.8.EXTOSC0 Register Memory Map.............................................................................. 359
20. External Regulator (EXTVREG0) .................................................................................... 360
20.1.External Regulator Features ...................................................................................... 360
20.2.Overview ....................................................................................................................361
20.3.Operating Modes ....................................................................................................... 361
20.4.Current Sensing ......................................................................................................... 363
20.5.Current Limiting..........................................................................................................365
20.6.Foldback Limiting ....................................................................................................... 366
20.7.Regulator Stability......................................................................................................367
20.8.Configuring the External Regulator............................................................................ 368
20.9.EXTVREG0 Registers................................................................................................ 369
20.10.EXTVREG0 Register Memory Map ......................................................................... 376
21. Flash Controller (FLASHCTRL0) .................................................................................... 378
21.1.Flash Controller Features .......................................................................................... 378
21.2.Overview ....................................................................................................................379
21.3.Flash Read Control .................................................................................................... 379
21.4.Flash Write and Erase Control................................................................................... 380
21.5.FLASHCTRL0 Registers............................................................................................ 383
21.6.FLASHCTRL0 Register Memory Map........................................................................ 389
22. Inter-Integrated Circuit Bus (I2C0 and I2C1) ................................................................. 391
22.1.I2C Features ..............................................................................................................391
22.2.I2C Protocol ............................................................................................................... 392
22.3.Clocking ..................................................................................................................... 396
22.4.Operational Modes..................................................................................................... 396
22.5.Error Handling............................................................................................................407
22.6.Additional Features .................................................................................................... 408
22.7.Debug Mode .............................................................................................................. 409
22.8.DMA Configuration and Usage .................................................................................. 410
22.9.I2C0 and I2C1 Registers............................................................................................ 415
22.10.I2Cn Register Memory Map ..................................................................................... 431
Rev. 1.0
5
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