FLEX 6000
®
Programmable Logic
Device Family
Data Sheet
March 2001, ver. 4.1
Features...
■
■
■
Provides an ideal low-cost, programmable alternative to high-
volume gate array applications and allows fast design changes
during prototyping or design testing
Product features
–
Register-rich, look-up table- (LUT-) based architecture
–
OptiFLEX
®
architecture that increases device area efficiency
–
Typical gates ranging from 5,000 to 24,000 gates (see
Table 1)
–
Built-in low-skew clock distribution tree
–
100% functional testing of all devices; test vectors or scan chains
are not required
System-level features
–
In-circuit reconfigurability (ICR) via external configuration
device or intelligent controller
–
5.0-V devices are fully compliant with peripheral component
interconnect Special Interest Group (PCI SIG)
PCI Local Bus
Specification, Revision 2.2
–
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
–
MultiVolt
TM
I/O interface operation, allowing a device to bridge
between systems operating at different voltages
–
Low power consumption (typical specification less than 0.5 mA
in standby mode)
–
3.3-V devices support hot-socketing
Table 1. FLEX 6000 Device Features
Feature
Typical gates
(1)
Logic elements (LEs)
Maximum I/O pins
Supply voltage (V
CCINT
)
Note:
(1)
The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.
EPF6010A
10,000
880
102
3.3 V
EPF6016
16,000
1,320
204
5.0 V
EPF6016A
16,000
1,320
171
3.3 V
EPF6024A
24,000
1,960
218
3.3 V
Altera Corporation
A-DS-F6000-04.1
1
FLEX 6000 Programmable Logic Device Family Data Sheet
...and More
Features
■
■
■
■
■
Powerful I/O pins
–
Individual tri-state output enable control for each pin
–
Programmable output slew-rate control to reduce switching
noise
–
Fast path from register to I/O pin for fast clock-to-output time
Flexible interconnect
–
FastTrack
®
Interconnect continuous routing structure for fast,
predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed, high-fan-
in logic functions (automatically used by software tools and
megafunctions)
–
Tri-state emulation that implements internal tri-state networks
–
Four low-skew global paths for clock, clear, preset, or logic
signals
Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs, Sun
SPARCstations, and HP 9000 Series 700/800
Flexible package options
–
Available in a variety of packages with 100 to 256 pins, including
the innovative FineLine BGA
TM
packages (see
Table 2)
–
SameFrame
TM
pin-compatibility (with other FLEX
®
6000 devices)
across device densities and pin counts
–
Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and
ball-grid array (BGA) packages (see
Table 2)
–
Footprint- and pin-compatibility with other FLEX 6000 devices
in the same package
Additional design entry and simulation support provided by
EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules
(LPM), Verilog HDL, VHDL, DesignWare components, and other
interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, VeriBest, and Viewlogic
Table 2. FLEX 6000 Package Options & I/O Pin Count
Device
EPF6010A
EPF6016
EPF6016A
EPF6024A
81
81
100-Pin
TQFP
71
100-Pin
FineLine BGA
144-Pin
TQFP
102
117
117
117
208-Pin
PQFP
171
171
171
240-Pin
PQFP
199
199
256-Pin
BGA
204
256-pin
FineLine BGA
171
218
219
2
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
General
Description
The Altera
®
FLEX 6000 programmable logic device (PLD) family provides
a low-cost alternative to high-volume gate array designs. FLEX 6000
devices are based on the OptiFLEX architecture, which minimizes die size
while maintaining high performance and routability. The devices have
reconfigurable SRAM elements, which give designers the flexibility to
quickly change their designs during prototyping and design testing.
Designers can also change functionality during operation via in-circuit
reconfiguration.
FLEX 6000 devices are reprogrammable, and they are 100% tested prior to
shipment. As a result, designers are not required to generate test vectors
for fault coverage purposes, allowing them to focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different gate array designs. FLEX 6000 devices are
configured on the board for the specific functionality required.
Table 3
shows FLEX 6000 performance for some common designs. All
performance values shown were obtained using Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 3. FLEX 6000 Device Performance for Common Designs
Application
LEs Used
-1 Speed
Grade
16-bit loadable counter
16-bit accumulator
24-bit accumulator
16-to-1 multiplexer (pin-to-pin)
(1)
16
×
16 multiplier with a 4-stage pipeline
Note:
(1)
This performance value is measured as a pin-to-pin delay.
Performance
-2 Speed
Grade
153
153
123
13.4
67
Units
-3 Speed
Grade
133
133
108
16.6
58
MHz
MHz
MHz
ns
MHz
16
16
24
10
592
172
172
136
12.1
84
Altera Corporation
3
FLEX 6000 Programmable Logic Device Family Data Sheet
Table 4
shows FLEX 6000 performance for more complex designs.
Table 4. FLEX 6000 Device Performance for Complex Designs
Application
LEs Used
-1 Speed
Grade
8-bit, 16-tap parallel finite impulse response
(FIR) filter
8-bit, 512-point fast Fourier transform (FFT)
function
a16450
universal asynchronous
receiver/transmitter (UART)
PCI bus target with zero wait states
Note:
(1)
Note (1)
Performance
-2 Speed
Grade
80
89
53
30
49
Units
-3 Speed
Grade
72
109
43
25
42
MSPS
µS
MHz
MHz
MHz
599
1,182
487
609
94
75
63
36
56
The applications in this table were created using Altera MegaCore
TM
functions
.
FLEX 6000 devices are supported by Altera development systems; a
single, integrated package that offers schematic, text (including AHDL),
and waveform design entry, compilation and logic synthesis, full
simulation and worst-case timing analysis, and device configuration. The
Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL,
and other interfaces for additional design entry and simulation support
from other industry-standard PC- and UNIX workstation-based EDA
tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development systems include DesignWare
functions that are optimized for the FLEX 6000 architecture.
The Altera development system runs on Windows-based PCs, Sun
SPARCstations, and HP 9000 Series 700/800.
f
See the
MAX+PLUS II Programmable Logic Development System & Software
Data Sheet
and the
Quartus Programmable Logic Development System &
Software Data Sheet
for more information.
4
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Functional
Description
The FLEX 6000 OptiFLEX architecture consists of logic elements (LEs).
Each LE includes a 4-input look-up table (LUT), which can implement any
4-input function, a register, and dedicated paths for carry and cascade
chain functions. Because each LE contains a register, a design can be easily
pipelined without consuming more LEs. The specified gate count for
FLEX 6000 devices includes all LUTs and registers.
LEs are combined into groups called logic array blocks (LABs); each LAB
contains 10 LEs. The Altera software automatically places related LEs into
the same LAB, minimizing the number of required interconnects. Each
LAB can implement a medium-sized block of logic, such as a counter or
multiplexer.
Signal interconnections within FLEX 6000 devices—and to and from
device pins—are provided via the routing structure of the FastTrack
Interconnect. The routing structure is a series of fast, continuous row and
column channels that run the entire length and width of the device. Any
LE or pin can feed or be fed by any other LE or pin via the FastTrack
Interconnect. See “FastTrack Interconnect” on
page 17
of this data sheet
for more information.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer. Each IOE is placed next to an LAB, where it can
be driven by the local interconnect of that LAB. This feature allows fast
clock-to-output times of less than 8 ns when a pin is driven by any of the
10 LEs in the adjacent LAB. Also, any LE can drive any pin via the row and
column interconnect. I/O pins can drive the LE registers via the row and
column interconnect, providing setup times as low as 2 ns and hold times
of 0 ns. IOEs provide a variety of features, such as JTAG BST support,
slew-rate control, and tri-state buffers.
Figure 1
shows a block diagram of the FLEX 6000 OptiFLEX architecture.
Each group of ten LEs is combined into an LAB, and the LABs are
arranged into rows and columns. The LABs are interconnected by the
FastTrack Interconnect. IOEs are located at the end of each FastTrack
Interconnect row and column.
Altera Corporation
5
FPGA/CPLD
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