Stratix II GX Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SIIGX5V1-4.4
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
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expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest ver-
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.
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Contents
Section I. Stratix II GX Device Data Sheet
Chapter 1. Introduction
Features ................................................................................................................................................... 1–1
Referenced Document ........................................................................................................................... 1–5
Document Revision History ................................................................................................................. 1–5
Chapter 2. Stratix II GX Architecture
Transceivers ............................................................................................................................................ 2–1
Transmitter Path ............................................................................................................................... 2–4
Receiver Path ................................................................................................................................... 2–14
Loopback Modes ............................................................................................................................ 2–30
Transceiver Clocking ..................................................................................................................... 2–35
Other Transceiver Features ........................................................................................................... 2–41
Logic Array Blocks .............................................................................................................................. 2–44
LAB Interconnects .......................................................................................................................... 2–45
LAB Control Signals ....................................................................................................................... 2–46
Adaptive Logic Modules .................................................................................................................... 2–48
ALM Operating Modes ................................................................................................................. 2–50
Arithmetic Mode ............................................................................................................................ 2–55
Shared Arithmetic Mode ............................................................................................................... 2–58
Shared Arithmetic Chain ............................................................................................................... 2–60
Register Chain ................................................................................................................................. 2–61
Clear and Preset Logic Control .................................................................................................... 2–63
MultiTrack Interconnect ..................................................................................................................... 2–63
TriMatrix Memory ............................................................................................................................... 2–69
M512 RAM Block ............................................................................................................................ 2–70
M4K RAM Blocks ........................................................................................................................... 2–73
M-RAM Block ................................................................................................................................. 2–75
Digital Signal Processing (DSP) Block .............................................................................................. 2–81
Modes of Operation ....................................................................................................................... 2–85
DSP Block Interface ........................................................................................................................ 2–85
PLLs and Clock Networks .................................................................................................................. 2–89
Global and Hierarchical Clocking ................................................................................................ 2–89
Enhanced and Fast PLLs ............................................................................................................... 2–97
Enhanced PLLs ............................................................................................................................. 2–109
Fast PLLs ........................................................................................................................................ 2–109
I/O Structure ...................................................................................................................................... 2–110
Double Data Rate I/O Pins ......................................................................................................... 2–118
External RAM Interfacing ........................................................................................................... 2–122
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Contents
Stratix II GX Device Handbook, Volume 1
Programmable Drive Strength ...................................................................................................
Open-Drain Output ......................................................................................................................
Bus Hold ........................................................................................................................................
Programmable Pull-Up Resistor ................................................................................................
Advanced I/O Standard Support ..............................................................................................
On-Chip Termination ..................................................................................................................
MultiVolt I/O Interface ...............................................................................................................
High-Speed Differential I/O with DPA Support ..........................................................................
Dedicated Circuitry with DPA Support ....................................................................................
Fast PLL and Channel Layout ....................................................................................................
Referenced Documents .....................................................................................................................
Document Revision History .............................................................................................................
2–124
2–125
2–125
2–126
2–126
2–130
2–133
2–136
2–138
2–141
2–142
2–143
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support ............................................................................... 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–3
Configuration ......................................................................................................................................... 3–3
Operating Modes .............................................................................................................................. 3–4
Configuration Schemes ................................................................................................................... 3–6
Device Security Using Configuration Bitstream Encryption ..................................................... 3–7
Device Configuration Data Decompression ................................................................................. 3–7
Remote System Upgrades ............................................................................................................... 3–8
Configuring Stratix II GX FPGAs with JRunner .......................................................................... 3–8
Programming Serial Configuration Devices with SRunner ....................................................... 3–9
Configuring Stratix II FPGAs with the MicroBlaster Driver ..................................................... 3–9
PLL Reconfiguration ........................................................................................................................ 3–9
Temperature Sensing Diode (TSD) ................................................................................................... 3–10
Automated Single Event Upset (SEU) Detection ............................................................................ 3–12
Custom-Built Circuitry .................................................................................................................. 3–12
Software Interface ........................................................................................................................... 3–12
Referenced Documents ....................................................................................................................... 3–13
Document Revision History ............................................................................................................... 3–13
Chapter 4. DC and Switching Characteristics
Operating Conditions ........................................................................................................................... 4–1
Absolute Maximum Ratings ........................................................................................................... 4–1
Recommended Operating Conditions .......................................................................................... 4–2
Transceiver Block Characteristics .................................................................................................. 4–3
DC Electrical Characteristics ........................................................................................................ 4–42
I/O Standard Specifications ......................................................................................................... 4–43
Bus Hold Specifications ................................................................................................................. 4–56
On-Chip Termination Specifications ........................................................................................... 4–56
Pin Capacitance .............................................................................................................................. 4–58
Power Consumption ........................................................................................................................... 4–59
Timing Model ....................................................................................................................................... 4–59
Preliminary and Final Timing ...................................................................................................... 4–59
I/O Timing Measurement Methodology .................................................................................... 4–60
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Stratix II GX Device Handbook, Volume 1
Contents
Internal Timing Parameters .......................................................................................................... 4–69
Stratix II GX Clock Timing Parameters ....................................................................................... 4–76
Clock Network Skew Adders ....................................................................................................... 4–81
IOE Programmable Delay ............................................................................................................. 4–82
Default Capacitive Loading of Different I/O Standards .......................................................... 4–83
I/O Delays ....................................................................................................................................... 4–84
Maximum Input and Output Clock Toggle Rate ....................................................................... 4–98
Duty Cycle Distortion ....................................................................................................................... 4–118
DCD Measurement Techniques ................................................................................................. 4–118
High-Speed I/O Specifications ........................................................................................................ 4–126
PLL Timing Specifications ................................................................................................................ 4–130
External Memory Interface Specifications ..................................................................................... 4–132
JTAG Timing Specifications ............................................................................................................. 4–134
Referenced Documents ..................................................................................................................... 4–136
Document Revision History ............................................................................................................. 4–137
Chapter 5. Reference and Ordering Information
Device Pin-Outs .....................................................................................................................................
Ordering Information ...........................................................................................................................
Referenced Documents .........................................................................................................................
Document Revision History .................................................................................................................
5–1
5–1
5–2
5–2
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