MachXO3™ Family Data Sheet
Advance DS1047 Version 1.1, July 2014
MachXO3 Family Data Sheet
Introduction
June 2014
Advance Data Sheet DS1047
Features
Solutions
• Smallest footprint, lowest power, high data
throughput bridging solutions for mobile applica-
tions
• Optimized footprint, logic density, IO count, IO
performance devices for IO management and
logic applications
• High IO/logic, lowest cost/IO, high IO devices for
IO expansion applications
Flexible On-Chip Clocking
• Eight primary clocks
• Up to two edge clocks for high-speed I/O inter-
faces (top and bottom sides only)
• Up to two analog PLLs per device with frac-
tional-n frequency synthesis
- Wide input frequency range (7 MHz to 400
MHz)
Flexible Architecture
• Logic Density ranging from 640 to 6.9K LUT4
• High IO to LUT ratio with up to 335 IO pins
Non-volatile, Multi-time Programmable
• Instant-on
- Powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I
2
C
• Optional dual boot with external SPI memory
Advanced Packaging
• 0.4 mm pitch: 1K to 4K densities in very small
footprint WLCSP (2.5 mm x 2.5 mm to 3.8 mm x
3.8 mm) with 28 to 63 IOs
• 0.5 mm pitch: 640 to 6.9K LUT densities in 6 mm
x 6 mm to 10 mm x 10 mm BGA packages with
up to 281 IOs
• 0.8mm pitch: 1K to 6.9K densities with up to 335
IOs in BGA packages
TransFR Reconfiguration
• In-field logic update while IO holds the system
state
Enhanced System Level Support
• On-chip hardened functions: SPI, I
2
C, timer/
counter
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• Single power supply with extended operating
range
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
Pre-Engineered Source Synchronous I/O
•
•
•
•
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRx2, DDRx4
High Performance, Flexible I/O Buffer
• Programmable sysIO
TM
buffer supports wide
range of interfaces:
- LVCMOS 3.3/2.5/1.8/1.5/1.2
- LVTTL
- LVDS, Bus-LVDS, MLVDS, LVPECL
- MIPI D-PHY Emulated
- Schmitt trigger inputs, up to 0.5 V hysteresis
• Ideal for IO bridging applications
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
Applications
•
•
•
•
•
Consumer Electronics
Compute and Storage
Wireless Communications
Industrial Control Systems
Automotive System
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1047
Introduction_0.4
Introduction
MachXO3 Family Data Sheet
Table 1-1. MachXO3L Family Selection Guide
Features
LUTs
Distributed RAM (Kbits)
EBR SRAM (Kbits)
Number of PLLs
Hardened Functions:
I2C
SPI
Timer/Counter
Oscillator
MIPI D-PHY Support
Multi Time Programmable NVCM
Packages
36-ball WLCSP
1
(2.5 mm x 2.5 mm, 0.4 mm)
49-ball WLCSP
1
(3.2 mm x 3.2 mm, 0.4 mm)
81-ball WLCSP
1
(3.8 mm x 3.8 mm, 0.4 mm)
121-ball csfBGA
1
(6 mm x 6 mm, 0.5 mm)
256-ball csfBGA
1
(9 mm x 9 mm, 0.5 mm)
324-ball csfBGA
1
(10 mm x 10 mm, 0.5 mm)
256-ball caBGA
2
(14 mm x 14mm, 0.8 mm)
324-ball caBGA
2
(15 mm x 15 mm, 0.8 mm)
400-ball caBGA
2
(17 mm x 17 mm, 0.8 mm)
1. Package is only available for E=1.2 V devices.
2. Package is only available for C=2.5 V/3.3 V devices.
XO3L-640
640
5
64
1
2
1
1
1
Yes
Yes
XO3L-1300
1300
10
64
1
2
1
1
1
Yes
Yes
XO3L-2100
2100
16
74
1
2
1
1
1
Yes
Yes
IO
XO3L-4300
4300
34
92
2
2
1
1
1
Yes
Yes
XO3L-6900
6900
54
240
2
2
1
1
1
Yes
Yes
28
38
63
100
100
206
100
206
267
206
206
279
100
206
267
206
279
335
206
281
206
279
335
Introduction
MachXO3
TM
device family is an Ultra-Low Density family that supports the most advanced programmable bridging
and IO expansion. It has the breakthrough IO density and the lowest cost per IO. The device IO features have the
integrated support for latest industry standard IO.
The MachXO3L family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640
to 6900 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature
Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous
I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly
used functions such as SPI controller, I
2
C controller and timer/counter. These features allow these devices to be
used in low cost, high volume consumer and system applications.
The MachXO3L devices are designed on a 65nm non-volatile low power process. The device architecture has sev-
eral features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs
and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low
static power for all members of the family.
1-2
Introduction
MachXO3 Family Data Sheet
The MachXO3L devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the
fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or
2.5 V. E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage
both C and E are functionally compatible with each other.
The MachXO3L PLDs are available in a broad range of advanced halogen-free packages ranging from the space
saving 2.5 x 2.5 mm WLCSP to the 17 x 17 mm caBGA. MachXO3L devices support density migration within the
same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.
The MachXO3L devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-
bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-
down and bus-keeper features are controllable on a “per-pin” basis.
A user-programmable internal oscillator is included in MachXO3L devices. The clock output from this oscillator may
be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-
ilar state machines.
The MachXO3L devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices
can also configure themselves from external SPI Flash or be configured by an external master through the JTAG
test access port or through the I
2
C port. Additionally, MachXO3L devices support dual-boot capability (using exter-
nal Flash memory) and remote field upgrade (TransFR) capability.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the
MachXO3L family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L. Lattice
design tools use the synthesis tool output along with the user-specified preferences and constraints to place and
route the design in the MachXO3L device. These tools extract the timing from the routing and back-annotate it into
the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of
reference designs licensed free of charge, optimized for the MachXO3L PLD family. By using these configurable
soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-3
MachXO3 Family Data Sheet
Architecture
June 2014
Advance Data Sheet DS1047
Architecture Overview
The MachXO3L family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The
larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM
(EBRs). Figures 2-1 and 2-2 show the block diagrams of the various family members.
Figure 2-1. Top View of the MachXO Device
Embedded Function
Block (EFB)
NVCM1
sysCLOCK PLL
sysMEM Embedded
Block RAM (EBR)
Configuration NVCM0
PIOs Arranged into
sysIO Banks
Programmable Function Units
with Distributed RAM (PFUs)
Note:
MachXO3L-640 is similar to MachXO3L-1300. MachXO3L-640 has a lower LUT count.
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1047
Introduction_0.2
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