Stratix GX FPGA Family
December 2004, ver. 2.2
Data Sheet
Introduction
The Stratix
®
GX family of devices is Altera’s second FPGA family to
combine high-speed serial transceivers with a scalable, high-performance
logic array. Stratix GX devices include 4 to 20 high-speed transceiver
channels, each incorporating clock data recovery (CDR) technology and
embedded SERDES capability at data rates of up to 3.1875 gigabits per
second (Gbps). These transceivers are grouped by four-channel
transceiver blocks, and are designed for low power consumption and
small die size. The Stratix GX FPGA technology is built upon the Stratix
architecture, and offers a 1.5-V logic array with unmatched performance,
flexibility, and time-to-market capabilities. This scalable,
high-performance architecture makes Stratix GX devices ideal for
high-speed backplane interface, chip-to-chip, and communications
protocol-bridging applications.
■
Features
Transceiver block features are as follows:
●
High-speed serial transceiver channels with CDR provides
500-megabits per second (Mbps) to 3.1875-Gbps full-duplex
operation
●
Devices are available with 4, 8, 16, or 20 high-speed serial
transceiver channels providing up to 127.5 Gbps of full-duplex
serial bandwidth
●
Support for transceiver-based protocols, including 10 Gigabit
Ethernet attachment unit interface (XAUI), Gigabit Ethernet
(GigE), and SONET/SDH
●
Compatible with PCI Express, SMPTE 292M, Fibre Channel, and
Serial RapidIO I/O standards
●
Programmable differential output voltage (V
OD
), pre-emphasis,
and equalization settings for improved signal integrity
●
Individual transmitter and receiver channel power-down
capability implemented automatically by the Quartus
®
II
software for reduced power consumption during non-operation
●
Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, and 20-bit wide data paths
●
1.5-V pseudo current mode logic (PCML) for 500 Mbps to
3.1875 Gbps
●
Support for LVDS, LVPECL, and 3.3-V PCML on reference
clocks and receiver input pins (AC-coupled)
●
Built-in self test (BIST)
●
Hot insertion/removal protection circuitry
Altera Corporation
DS-STXGX-2.2
1
Preliminary
Stratix GX FPGA Family
●
●
●
●
●
Pattern detector and word aligner supports programmable
patterns
8B/10B encoder/decoder performs 8- to 10-bit encoding and 10-
to 8-bit decoding
Rate matcher compliant with IEEE 802.3-2002 for GigE mode
and with IEEE 802-3ae for XAUI mode
Channel bonding compliant with IEEE 802.3ae (for XAUI mode
only)
Device can bypass some transceiver block features if necessary
■
FPGA features are as follows:
●
10,570 to 41,250 logic elements (LEs); see
Table 1
●
Up to 3,423,744 RAM bits (427,968 bytes) available without
reducing logic resources
●
TriMatrix
™
memory consisting of three RAM block sizes to
implement true dual-port memory and first-in-out (FIFO)
buffers
●
Up to 16 global clock networks with up to 22 regional clock
networks per device region
●
High-speed DSP blocks provide dedicated implementation of
multipliers (faster than 300 MHz), multiply-accumulate
functions, and finite impulse response (FIR) filters
●
Up to eight general usage phase-locked loops (four enhanced
PLLs and four fast PLLs) per device provide spread spectrum,
programmable bandwidth, clock switchover, real-time PLL
reconfiguration, and advanced multiplication and phase
shifting
●
Support for numerous single-ended and differential I/O
standards
●
High-speed source-synchronous differential I/O support on up
to 45 channels for 1-Gbps performance
●
Support for source-synchronous bus standards, including
10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV,
Network Packet Streaming Interface (NPSI), HyperTransport
TM
technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
●
Support for high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII)
SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM
(FCRAM), and single data rate (SDR) SDRAM
●
Support for multiple intellectual property megafunctions from
Altera
®
MegaCore
®
functions and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions
●
Support for remote configuration updates
●
Dynamic phase alignment on LVDS receiver channels
2
Preliminary
Altera Corporation
Features
Table 1. Stratix GX Device Features
Feature
LEs
Transceiver channels
Source-synchronous channels
M512 RAM blocks (32
×
18 bits)
M4K RAM blocks (128
×
36 bits)
M-RAM blocks (4K
×
144 bits)
Total RAM bits
Digital signal processing (DSP) blocks
Embedded multipliers
(1)
PLLs
Note to
Table 1:
(1)
This parameter lists the total number of 9- × 9-bit multipliers for each device. For the total number of 18- × 18-bit
multipliers per device, divide the total number of 9- × 9-bit multipliers by 2. For the total number of 36- × 36-bit
multipliers per device, decide the total number of 9- × 9-bit multipliers by 8.
EP1SGX10C
EP1SGX10D
10,570
4, 8
22
94
60
1
920,448
6
48
4
EP1SGX25C
EP1SGX25D
EP1SGX25F
25,660
4, 8, 16
39
224
138
2
1,944,576
10
80
4
EP1SGX40D
EP1SGX40G
41,250
8, 20
45
384
183
4
3,423,744
14
112
8
Stratix GX devices are available in space-saving FineLine BGA
®
packages
(refer to
Tables 2
and
3),
and in multiple speed grades (refer to
Table 4).
Stratix GX devices support vertical migration within the same package
(that is, the designer can migrate between the EP1SGX10C and
EP1SGX25C devices in the 672-pin FineLine BGA package). See the
Stratix GX device pin tables for more information. Vertical migration
means that designers can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package
across device densities. For I/O pin migration across densities, the
designer must cross-reference the available I/O pins using the device pin-
outs for all planned densities of a given package type, to identify which
I/O pins it is possible to migrate. The Quartus II software can
automatically cross reference and place all pins for migration when given
a device migration list.
Table 2. Stratix GX Package Options & I/O Pin Counts (Part 1
of 2)
Note (1)
Device
EP1SGX10C
EP1SGX10D
EP1SGX25C
672-Pin FineLine BGA
362
362
455
1,020-Pin FineLine BGA
Altera Corporation
3
Preliminary
Stratix GX FPGA Family
Table 2. Stratix GX Package Options & I/O Pin Counts (Part 2
of 2)
Note (1)
Device
EP1SGX25D
EP1SGX25F
EP1SGX40D
EP1SGX40G
Note to
Table 2:
(1)
The number of I/O pins listed for each package includes dedicated clock pins and
dedicated fast I/O pins. However, these numbers do not include high-speed or
clock reference pins for high-speed I/O standards.
672-Pin FineLine BGA
455
1,020-Pin FineLine BGA
607
607
624
624
Table 3. Stratix GX FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm
2
)
Length
×
width (mm
×
mm)
672 Pin
1.00
729
27
×
27
1,020 Pin
1.00
1,089
33
×
33
Table 4. Stratix GX Device Speed Grades
Device
EP1SGX10
EP1SGX25
EP1SGX40
672-Pin FineLine BGA
-5, -6, -7
-5, -6, -7
1,020-pin FineLine BGA
-5, -6, -7
-5, -6, -7
High-Speed I/O
Interface
Functional
Description
The Stratix GX device family supports high-speed serial transceiver
blocks with CDR circuitry as well as source-synchronous interfaces. The
channels on the right side of the device use an embedded circuit
dedicated for receiving and transmitting high-speed serial data streams
to and from the system board. These channels are clustered in a
four-channel serial transceiver building block and deliver high-speed
bidirectional point-to-point data transmissions to provide up to
3.1875 Gbps of full-duplex data transmission per channel. The channels
on the left side of the device support source-synchronous data transfers
at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport
technology I/O standards.
Figure 1
shows the Stratix GX I/O blocks. The
differential source-synchronous serial interface is described in
“Principles of SERDES Operation” on page 47
and the high-speed serial
interface is described in
“Transceiver Blocks” on page 8.
4
Preliminary
Altera Corporation
FPGA Functional Description
Figure 1. Stratix GX I/O Blocks
DQST9
PLL7
Note (1)
DQST5
9
PLL5
10
DQST4
PLL11
DQST3
DQST2
Bank 4
DQST8
DQST7
Bank 3
DQST6
DQST1
DQST0
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4
VREF1B2 VREF2B2 VREF3B2 VREF4B2
I/O Bank 13
(5)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins
(3)
Bank 2
(4)
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards
(2)
I/O Bank 14
(5)
PLL1
PLL2
VREF1B1 VREF2B1 VREF3B1 VREF4B1
I/O Banks 1 and 2 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X, and AGP 1
×
/2
×
1.5-V PCML
(5)
I/O Bank 17
(5)
Bank 1
(4)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins
(3)
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards
(2)
I/O Bank 16
(5)
I/O Bank 15
(5)
Bank 8
11
DQSB6
DQSB5
12
PLL12
DQSB4
DQSB3
Bank 7
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
PLL8
DQSB9
DQSB8
DQSB7
PLL6
DQSB2
DQSB1
DQSB0
Notes to
Figure 1:
(1)
(2)
(3)
(4)
(5)
Figure 1
is a top view of the Stratix GX silicon die.
Banks 9 through 12 are enhanced PLL external clock output banks.
If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the
I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1×/2×.
For guidelines for placing single-ended I/O pads next to differential I/O pads, see the
Selectable I/O Standards in
Stratix & Stratix GX Devices
chapter in the
Stratix Device Handbook,
Volume 2.
These I/O banks in Stratix GX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on reference
clocks and receiver input pins (AC coupled).
FPGA Functional
Description
Stratix GX devices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provide signal interconnects
between logic array blocks (LABs), memory block structures, and DSP
blocks.
Altera Corporation
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Preliminary
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