Freescale Semiconductor
Technical Data
Document Number: MRFE6VP6300H
Rev. 1, 7/2011
RF Power Field Effect Transistors
High Ruggedness N--Channel
Enhancement--Mode Lateral MOSFETs
These high ruggedness devices are designed for use in high VSWR industrial
(including laser and plasma exciters), broadcast (analog and digital), aerospace
and radio/land mobile applications. They are unmatched input and output
designs allowing wide frequency range utilization, between 1.8 and 600 MHz.
•
Typical Performance: V
DD
= 50 Volts, I
DQ
= 100 mA
Signal Type
Pulsed (100
μsec,
20% Duty Cycle)
CW
P
out
(W)
300 Peak
300 Avg.
f
(MHz)
230
130
G
ps
(dB)
26.5
25.0
η
D
(%)
74.0
80.0
IRL
(dB)
--16
--15
MRFE6VP6300HR3
MRFE6VP6300HSR3
1.8-
-600 MHz, 300 W, 50 V
LATERAL N-
-CHANNEL
BROADBAND
RF POWER MOSFETs
•
Capable of Handling a Load Mismatch of 65:1 VSWR, @ 50 Vdc, 230 MHz,
at all Phase Angles
•
300 Watts CW Output Power
•
300 Watts Pulsed Peak Power, 20% Duty Cycle, 100
μsec
•
Capable of 300 Watts CW Operation
Features
•
Unmatched Input and Output Allowing Wide Frequency Range Utilization
•
Device can be used Single--Ended or in a Push--Pull Configuration
•
Qualified Up to a Maximum of 50 V
DD
Operation
•
Characterized from 30 V to 50 V for Extended Power Range
•
Suitable for Linear Application with Appropriate Biasing
•
Integrated ESD Protection
•
Greater Negative Gate--Source Voltage Range for Improved Class C Operation
•
Characterized with Series Equivalent Large--Signal Impedance Parameters
•
RoHS Compliant
•
NI--780--4 in Tape and Reel. R3 Suffix = 250 Units, 56 mm Tape Width,
13 inch Reel. For R5 Tape and Reel options, see p. 14.
•
NI--780S--4 in Tape and Reel. R3 Suffix = 250 Units, 32 mm Tape Width,
13 inch Reel. For R5 Tape and Reel options, see p. 14.
Table 1. Maximum Ratings
Rating
Drain--Source Voltage
Gate--Source Voltage
Storage Temperature Range
Case Operating Temperature
Total Device Dissipation @ T
C
= 25°C
Derate above 25°C
Operating Junction Temperature
(1,2)
Symbol
V
DSS
V
GS
T
stg
T
C
P
D
T
J
Value
--0.5, +130
--6.0, +10
--65 to +150
150
1050
5.26
225
Unit
Vdc
Vdc
°C
°C
W
W/°C
°C
CASE 465M-
-01, STYLE 1
NI-
-780-
-4
MRFE6VP6300HR3
CASE 465H-
-02, STYLE 1
NI-
-780S-
-4
MRFE6VP6300HSR3
RF
in
/V
GS
3
1 RF
out
/V
DS
RF
in
/V
GS
4
2 RF
out
/V
DS
(Top View)
Figure 1. Pin Connections
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
(4)
Pulsed: Case Temperature 75°C, 300 W Pulsed, 100
μsec
Pulse Width, 20% Duty Cycle,
50 Vdc, I
DQ
= 100 mA, 230 MHz
CW: Case Temperature 87°C, 300 W CW, 50 Vdc, I
DQ
= 1100 mA, 230 MHz
Symbol
Value
(2,3)
Unit
°C/W
Z
θJC
R
θJC
0.05
0.19
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access
MTTF calculators by product.
3. Refer to AN1955,
Thermal Measurement Methodology of RF Power Amplifiers.
Go to http://www.freescale.com/rf.
Select Documentation/Application Notes -- AN1955.
4. Same test circuit is used for both pulsed and CW.
©
Freescale Semiconductor, Inc., 2010--2011. All rights reserved.
MRFE6VP6300HR3 MRFE6VP6300HSR3
1
RF Device Data
Freescale Semiconductor
Table 3. ESD Protection Characteristics
Test Methodology
Human Body Model (per JESD22--A114)
Machine Model (per EIA/JESD22--A115)
Charge Device Model (per JESD22--C101)
Class
2 (Minimum)
B (Minimum)
IV (Minimum)
Table 4. Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Characteristic
Off Characteristics
(1)
Gate--Source Leakage Current
(V
GS
= 5 Vdc, V
DS
= 0 Vdc)
Drain--Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 50 mA)
Zero Gate Voltage Drain Leakage Current
(V
DS
= 50 Vdc, V
GS
= 0 Vdc)
Zero Gate Voltage Drain Leakage Current
(V
DS
= 100 Vdc, V
GS
= 0 Vdc)
On Characteristics
Gate Threshold Voltage
(1)
(V
DS
= 10 Vdc, I
D
= 480
μAdc)
Gate Quiescent Voltage
(V
DD
= 50 Vdc, I
D
= 100 mAdc, Measured in Functional Test)
Drain--Source On--Voltage
(1)
(V
GS
= 10 Vdc, I
D
= 1 Adc)
Dynamic Characteristics
(1)
Reverse Transfer Capacitance
(V
DS
= 50 Vdc
±
30 mV(rms)ac @ 1 MHz, V
GS
= 0 Vdc)
Output Capacitance
(V
DS
= 50 Vdc
±
30 mV(rms)ac @ 1 MHz, V
GS
= 0 Vdc)
Input Capacitance
(V
DS
= 50 Vdc, V
GS
= 0 Vdc
±
30 mV(rms)ac @ 1 MHz)
C
rss
C
oss
C
iss
—
—
—
0.8
76
188
—
—
—
pF
pF
pF
V
GS(th)
V
GS(Q)
V
DS(on)
1.7
2.0
—
2.2
2.5
0.25
2.7
3.0
—
Vdc
Vdc
Vdc
I
GSS
V
(BR)DSS
I
DSS
I
DSS
—
130
—
—
—
—
—
—
1
—
5
10
μAdc
Vdc
μAdc
μAdc
Symbol
Min
Typ
Max
Unit
Functional Tests
(In Freescale Test Fixture, 50 ohm system) V
DD
= 50 Vdc, I
DQ
= 100 mA, P
out
= 300 W Peak (60 W Avg.), f = 230 MHz,
Pulsed, 100
μsec
Pulse Width, 20% Duty Cycle
Power Gain
Drain Efficiency
Input Return Loss
VSWR 65:1 at all Phase Angles
Pulsed: P
out
= 300 W Peak (60 W Avg.), f = 230 MHz, Pulsed,
100
μsec
Pulse Width, 20% Duty Cycle
CW: P
out
= 300 W Avg., f = 130 MHz
1. Each side of device measured separately.
G
ps
η
D
IRL
25.0
72.0
—
26.5
74.0
--16
28.0
—
--9
dB
%
dB
Load Mismatch
(In Freescale Application Test Fixture, 50 ohm system) V
DD
= 50 Vdc, I
DQ
= 100 mA
Ψ
No Degradation in Output Power
MRFE6VP6300HR3 MRFE6VP6300HSR3
2
RF Device Data
Freescale Semiconductor
V
BIAS
+
C8
L1
C9
+
C14
+
C15
L2
C10
C11
C12
C13
+
C16
V
SUPPLY
C4
RF
INPUT
C5
C6
C7
R1
Z8
Z9
Z10
Z11
Z12
C20
C17
C18
C19
Z13
RF
OUTPUT
Z1
C1
Z2
Z3
Z4
Z5
Z6
Z7
DUT
C2
C3
Z1
Z2*
Z3*
Z4
Z5
Z6
Z7, Z8
0.352″ x 0.080″ Microstrip
1.780″ x 0.080″ Microstrip
0.576″ x 0.080″ Microstrip
0.220″ x 0.220″ Microstrip
0.322″ x 0.220″ Microstrip
0.168″ x 0.220″ Microstrip
0.282″ x 0.630″ Microstrip
Z9
Z10*
Z11*
Z12*
Z13
0.192″ x 0.170″ Microstrip
0.366″ x 0.170″ Microstrip
2.195″ x 0.170″ Microstrip
0.614″ x 0.170″ Microstrip
0.243″ x 0.080″ Microstrip
* Line length includes microstrip bends
Note: Same test circuit is used for both pulsed and CW.
Figure 2. MRFE6VP6300HR3(HSR3) Test Circuit Schematic
Table 5. MRFE6VP6300HR3(HSR3) Test Circuit Component Designations and Values
Part
C1, C20
C2
C3, C17
C4, C10
C5, C11
C6
C7
C8
C9
C12
C13
C14, C15, C16
C18, C19
L1
L2
R1
PCB
Description
15 pF Chip Capacitors
82 pF Chip Capacitor
91 pF Chip Capacitors
1000 pF Chip Capacitors
10K pF Chip Capacitors
0.1
μF,
50 V Chip Capacitor
2.2
μF,
100 V Chip Capacitor
10
μF,
35 V Tantalum Capacitor
2.2
μF,
100 V Chip Capacitor
0.1
μF,
100 V Chip Capacitor
0.01
μF,
100 V Chip Capacitor
220
μF,
100 V Electolytic Capacitors
18 pF Chip Capacitors
120 nH Inductor
17.5 nH Inductor
1000
Ω,
1/2 W Chip Resistor
0.030″,
ε
r
= 2.55
Part Number
ATC100B150JT500XT
ATC100B820JT500XT
ATC100B910JT500XT
ATC100B102JT50XT
ATC200B103KT50XT
CDR33BX104AKWS
HMK432B7225KM--T
T491D106K035AT
G2225X7R225KT3AB
C1812F104K1RAC
C1825C103K1GAC
MCGPR100V227M16X26--RH
ATC100B180JT500XT
1812SMS--R12JLC
GA3095--ALC
CRCW20101K00FKEF
AD255A
Manufacturer
ATC
ATC
ATC
ATC
ATC
AVX
Taiyo Yuden
Kemet
ATC
Kemet
Kemet
Multicomp
ATC
Coilcraft
Coilcraft
Vishay
Arlon
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
3
C8
C14
L1
C6
C5
C7
C15
C13
C12
C16
C9
C10
C11
C1
C4
C3
C2
R1
CUT OUT AREA
L2
C17
C18
C20
C19
MRFE6VP6300H/HS
Rev. 2
Figure 3. MRFE6VP6300HR3(HSR3) Test Circuit Component Layout
MRFE6VP6300HR3 MRFE6VP6300HSR3
4
RF Device Data
Freescale Semiconductor
TYPICAL CHARACTERISTICS — PULSED
1000
P
out
, OUTPUT POWER (dBm) PULSED
C
iss
C, CAPACITANCE (pF)
100
C
oss
10
60
59
58
57
56
55
54
53
26
V
DD
= 50 Vdc, I
DQ
= 100 mA, f = 230 MHz
Pulse Width = 100
μsec,
20% Duty Cycle
27
28
29
30
31
32
33
34
P3dB = 56.0 dBm (398 W)
P2dB = 55.8 dBm (380 W)
Ideal
P1dB = 55.4 dBm
(344 W)
Actual
1
Measured with
±30
mV(rms)ac @ 1 MHz
V
GS
= 0 Vdc
0
10
20
30
40
C
rss
0.1
50
V
DS
, DRAIN--SOURCE VOLTAGE (VOLTS)
P
in
, INPUT POWER (dBm) PULSED
Note:
Each side of device measured separately.
Figure 4. Capacitance versus Drain-
-Source Voltage
29
28
G
ps
, POWER GAIN (dB)
27
26
25
24
23
22
20
η
D
100
P
out
, OUTPUT POWER (WATTS) PULSED
20
600
G
ps
V
DD
= 50 Vdc, I
DQ
= 100 mA, f = 230 MHz
Pulse Width = 100
μsec,
20% Duty Cycle
90
80
G
ps
, POWER GAIN (dB)
70
60
50
40
30
η
D,
DRAIN EFFICIENCY (%)
29
28
27
26
25
24
23
22
21
20
19
0
Figure 5. Pulsed Output Power versus
Input Power
V
DD
= 50 Vdc, I
DQ
= 100 mA, f = 230 MHz
Pulse Width = 100
μsec,
20% Duty Cycle
50 V
40 V
35 V
V
DD
= 30 V
50
100
150
200
250
300
350
400
45 V
P
out
, OUTPUT POWER (WATTS) PULSED
Figure 6. Pulsed Power Gain and Drain Efficiency
versus Output Power
90
80
η
D,
DRAIN EFFICIENCY (%)
70
60
50
40
30
20
V
DD
= 50 Vdc, I
DQ
= 100 mA, f = 230 MHz
Pulse Width = 100
μsec,
20% Duty Cycle
0
50
100
150
200
250
300
350
400
V
DD
= 30 V
35 V
40 V
45 V
50 V
G
ps
, POWER GAIN (dB)
29
Figure 7. Pulsed Power Gain versus
Output Power
90
80
η
D
,
DRAIN EFFICIENCY (%)
V
DD
= 50 Vdc, I
DQ
= 100 mA, f = 230 MHz
28 Pulse Width = 100
μsec,
20% Duty Cycle
27
26
25
24
23
22
21
10
85_C
η
D
100
T
C
= --30_C
25_C
G
ps
85_C
25_C
--30_C 70
60
50
40
30
20
10
600
P
out
, OUTPUT POWER (WATTS) PULSED
P
out
, OUTPUT POWER (WATTS) PULSED
Figure 8. Pulsed Drain Efficiency versus
Output Power
Figure 9. Pulsed Power Gain and Drain Efficiency
versus Output Power
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
5
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