EURO
QUARTZ
11.4 x 9.6 x 2.5mm 6 pad SMD
DESCRIPTION
HPF62 series LVPECL output oscillators cover the frequency range
38MHz to 640MHz. The part contains a high 'Q' fundamental crystal
and utilizes a low jitter multiplier circuit. Integrated Phase jitter
0.4ps typical.
SPECIFICATION
Frequency Range:
Output Logic
Phase Noise:
Frequency Stability:
Operating Temp Range
Commercial:
Industrial:
Input Voltage:
Output Voltage
High '1':
Low '0':
HPF62 PECL OSCILLATORS
38.0MHz to 640.0MHz
OUTLINE & DIMENSIONS
38.0MHz to 640.0MHz
LVPECL
See table
See table
-10° to +70°C
-40° to +85°C
+2.5V or +3.3VDC ±5%
Vdd -1.025V min.
Vdd -1.620V max.
(RL = 50W to Vdd -2.0V)
Rise/Fall Times:
0.7ns typical
(20% Vdd to 80% Vdd)
Current Consumption (15pF load):
38MHz to 100MHz:
65mA max.
100.01 to 320MHz:
80mA max.
320.01 to 640MHz:
90mA max.
Load:
50W into Vdd-2.0V
Start-up Time:
5ms typ., 10ms max.
Duty Cycle:
50%±5% (at Vdd -1.3V)
Input Static Discharge Prot:
2kV min.
Storage Temperature Range:
-55°C to +150°C
Ageing:
±3ppm per year max., ±2ppm
thereafter. At T amb +25°C
Enable/Disable
No connection:
Both outputs enabled
Disable:
Both outputs are disabled when
control pad is taken below 0.3V
referenced to ground. Oscillator is
always 'on'. (Special request -
oscillator is off when disabled.)
Enable:
Both Outputs are enabled when
control pad is taken above 0.7 Vcc
referenced to ground.
ABSOLUTE MAXIMUM RATINGS
(Permanent
damage may be caused if operated beyond these limits.)
Supply Voltage Vdd:
+4.6V max.
Input Voltage Vi:
Vss -0.5 min., VDD +0.5V max.
Input Voltage Vo:
Vss -0.5 min., Vdd +0.5V max.
PHASE NOISE (156.250MHz)
Offset
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
dBc/Hz
-62
-92
-120
-132
-128
-140
-150
STABILITY OVER TEMPERATURE RANGE
Stability
±ppm
25
50
100
25
50
100
Temperature Range Order Code
°C
-10 to +70
-10 to +70
-10 to +70
-40 to +85
-40 to +85
-40 to +85
A
B
C
D
E
F
PART NUMBERS
HPF62 oscillator part numbers are derived as follows:
Example:
Supply Voltage
25 = 2.5VDC
3 = 3.3VDC
Series Designation
Package Style
621 or 622
Stability Code
(See table)
Frequency
3HPF621-A-250.000
JITTER (at Fr = 156.520MHz)
Integrated Phase Jitter:
0.4ps typical, 0.5ps max.
(12kHz to 20MHz)
Period Jitter (RMS):
3ps typical 5ps maximum
Period Jitter (peak to peak): 20ps typical 30ps maximum
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
FPGA/CPLD
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