MAC4DSM, MAC4DSN
Preferred Device
Triacs
Silicon Bidirectional Thyristors
Designed for high volume, low cost, industrial and consumer
applications such as motor control; process control; temperature, light
and speed control.
Features
http://onsemi.com
•
•
•
•
•
•
•
•
Small Size Surface Mount DPAK Package
Passivated Die for Reliability and Uniformity
Blocking Voltage to 800 V
On−State Current Rating of 4.0 Amperes RMS at 108°C
Low IGT
−
10 mA Maximum in 3 Quadrants
High Immunity to dv/dt
−
50 V/ms at 125°C
Epoxy Meets UL 94 V−0 @ 0.125 in
ESD Ratings: Human Body Model, 3B
u
8000 V
Machine Model, C
u
400 V
•
Pb−Free Packages are Available
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Peak Repetitive Off−State Voltage
(Note 1) (T
J
=
−40
to 125°C, Sine
Wave, 50 to 60 Hz, Gate Open)
MAC4DSM
MAC4DSN
On−State RMS Current
(Full Cycle Sine Wave, 60 Hz,
T
C
= 108°C)
Peak Non-Repetitive Surge Current
(One Full Cycle Sine Wave, 60 Hz,
T
J
= 125°C)
Circuit Fusing Consideration
(t = 8.3 msec)
Peak Gate Power
(Pulse Width
≤
10
msec,
T
C
= 108°C)
Average Gate Power
(t = 8.3 msec, T
C
= 108°C)
Peak Gate Current
(Pulse Width
≤
20
msec,
T
C
= 108°C)
Peak Gate Voltage
(Pulse Width
≤
20
msec,
T
C
= 108°C)
Operating Junction Temperature Range
Storage Temperature Range
Symbol
V
DRM,
V
RRM
600
800
I
T(RMS)
4.0
A
1
I
TSM
40
A
2
Value
Unit
V
1 2
3
TRIACS
4.0 AMPERES RMS
600
−
800 VOLTS
MT2
G
MT1
MARKING
DIAGRAMS
4
DPAK
CASE 369C
STYLE 6
YWW
AC
4DSxG
4
DPAK−3
CASE 369D
STYLE 6
3
Y
WW
AC4DSx
G
= Year
= Work Week
= Device Code
x= M or N
= Pb−Free Package
YWW
AC
4DSxG
I
2
t
P
GM
P
G(AV)
I
GM
V
GM
T
J
T
stg
6.6
2.0
1.0
4.0
5.0
−40
to 125
−40
to 150
A
2
sec
W
W
A
V
°C
°C
1
2
3
4
PIN ASSIGNMENT
Main Terminal 1
Main Terminal 2
Gate
Main Terminal 2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. V
DRM
and V
RRM
for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the device are exceeded.
©
Semiconductor Components Industries, LLC, 2009
January, 2009
−
Rev. 6
1
Publication Order Number:
MAC4DSM/D
MAC4DSM, MAC4DSN
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance,
−
Junction−to−Case
−
Junction−to−Ambient
−
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering Purposes (Note 3)
Symbol
R
qJC
R
qJA
R
qJA
T
L
Max
3.5
88
80
260
Unit
°C/W
°C
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(V
D
= Rated V
DRM
, V
RRM
; Gate Open)
ON CHARACTERISTICS
Peak On−State Voltage (Note 4)
(I
TM
=
±
6.0 A)
Gate Trigger Current (Continuous dc) (V
D
= 12 V, R
L
= 100
W)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
Gate Trigger Voltage (Continuous dc) (V
D
= 12 V, R
L
= 100
W)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
Gate Non−Trigger Voltage (Continuous dc) (V
D
= 12 V, R
L
= 100
W)
MT2(+), G(+); MT2(+), G(−); MT2(−), G(−)
T
J
= 125°C
Holding Current
(V
D
= 12 V, Gate Open, Initiating Current =
±
200 mA)
Latching Current (V
D
= 12 V, I
G
= 10 mA)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
DYNAMIC CHARACTERISTICS
Characteristic
Rate of Change of Commutating Current
(V
D
= 400 V, I
TM
= 3.5 A, Commutating dv/dt = 10 V/msec, Gate Open, T
J
= 125°C,
f = 500 Hz, CL = 5.0
mF,
LL = 20 mH, No Snubber) See Figure 16
Critical Rate of Rise of Off−State Voltage
(V
D
= 0.67 X Rated V
DRM
, Exponential Waveform, Gate Open, T
J
= 125°C)
Symbol
di/dt(c)
Min
3.0
Typ
4.0
Max
−
Unit
A/ms
V
TM
I
GT
−
1.3
1.6
V
mA
T
J
= 25°C
T
J
= 125°C
I
DRM,
I
RRM
−
−
−
−
0.01
2.0
mA
Symbol
Min
Typ
Max
Unit
2.9
2.9
2.9
0.5
0.5
0.5
0.2
2.0
4.0
5.0
7.0
0.7
0.65
0.7
0.4
5.5
10
10
10
1.3
1.3
1.3
−
15
V
GT
V
V
GD
I
H
I
L
V
mA
mA
−
−
−
6.0
10
6.0
30
30
30
dv/dt
50
175
−
V/ms
2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.
3. 1/8″ from case for 10 seconds.
4. Pulse Test: Pulse Width
≤
2.0 msec, Duty Cycle
≤
2%.
ORDERING INFORMATION
Device
MAC4DSM−001
MAC4DSM−001G
MAC4DSMT4
MAC4DSMT4G
MAC4DSN−001
MAC4DSN−001G
MAC4DSNT4
MAC4DSNT4G
Package Type
DPAK−3
DPAK−3
(Pb−Free)
DPAK
DPAK
(Pb−Free)
DPAK−3
DPAK−3
(Pb−Free)
DPAK
DPAK
(Pb−Free)
Package
369D
369D
369C
369C
369D
369D
369C
369C
Shipping
†
75 Units / Rail
75 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
75 Units / Rail
75 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
2
MAC4DSM, MAC4DSN
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Quadrant 1
MainTerminal 2 +
Symbol
V
DRM
I
DRM
V
RRM
I
RRM
V
TM
I
H
Parameter
Peak Repetitive Forward Off−State Voltage
Peak Forward Blocking Current
Peak Repetitive Reverse Off−State Voltage
Peak Reverse Blocking Current
Maximum On−State Voltage
Holding Current
Quadrant 3
MainTerminal 2
−
I
H
V
TM
I
RRM
at V
RRM
on state
I
H
V
TM
off state
+ Voltage
I
DRM
at V
DRM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
(+) MT2
Quadrant II
(−) I
GT
GATE
MT1
REF
(+) I
GT
GATE
MT1
REF
Quadrant I
I
GT
−
(−) MT2
(−) MT2
+ I
GT
Quadrant III
(−) I
GT
GATE
MT1
REF
(+) I
GT
GATE
MT1
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
Quadrant IV
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
http://onsemi.com
3
MAC4DSM, MAC4DSN
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (
°
C)
P(AV) , AVERAGE POWER DISSIPATION (WATTS)
125
6.0
180°
5.0
α
α
dc
120
a
= 30°
60°
90°
120°
90°
4.0
a
= CONDUCTION ANGLE
3.0
2.0
115
α
α
110
a
= CONDUCTION ANGLE
120°
180°
dc
3.5
4.0
a
= 30°
1.0
0
0
1.0
2.0
3.0
60°
105
0
0.5
1.0
1.5
2.0
2.5
3.0
I
T(RMS)
, RMS ON-STATE CURRENT (AMPS)
4.0
I
T(RMS)
, RMS ON-STATE CURRENT (AMPS)
Figure 1. RMS Current Derating
Figure 2. On−State Power Dissipation
IT, INSTANTANEOUS ON-STATE CURRENT (AMPS)
TYPICAL @ T
J
= 25°C
10
MAXIMUM @ T
J
= 125°C
r(t) , TRANSIENT RESISTANCE (NORMALIZED)
100
1.0
0.1
Z
qJC(t)
= R
qJC(t)
Sr(t)
1.0
MAXIMUM @ T
J
= 25°C
0.1
0
1.0
2.0
3.0
4.0
5.0
V
T
, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
0.01
0.1
1.0
10
100
1000
10 k
t, TIME (ms)
Figure 3. On−State Characteristics
Figure 4. Transient Thermal Response
18
VGT, GATE TRIGGER VOLTAGE(VOLTS)
Q3
I GT, GATE TRIGGER CURRENT (mA)
16
14
12
10
8.0
6.0
4.0
2.0
0
-50
-25
0
25
50
75
100
125
Q1
Q2
1.0
Q3
0.8
Q2
Q1
0.6
0.4
0.2
-50
-25
0
25
50
75
100
125
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. Typical Gate Trigger Current versus
Junction Temperature
Figure 6. Typical Gate Trigger Voltage versus
Junction Temperature
http://onsemi.com
4
MAC4DSM, MAC4DSN
14
12
IH , HOLDING CURRENT (mA)
10
MT2 NEGATIVE
8.0
6.0
4.0
2.0
0
-50
MT2 POSITIVE
IL, LATCHING CURRENT (mA)
20
Q1
15
Q3
10
25
Q2
5.0
0
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 7. Typical Holding Current versus
Junction Temperature
Figure 8. Typical Latching Current versus
Junction Temperature
1000
T
J
= 125°C
800
STATIC dv/dt (V/
m
s)
STATIC dv/dt (V/
m
s)
1200
T
J
= 125°C
1000
800
600
400
200
0
100
1000
R
G-MT1
, GATE-MT1 RESISTANCE (OHMS)
10 k
100
1000
R
G-MT1
, GATE-MT1 RESISTANCE (OHMS)
10 k
600 V
V
PK
= 400 V
600
400
600 V
200
0
800 V
V
PK
= 400 V
800 V
Figure 9. Exponential Static dv/dt versus
Gate−MT1 Resistance, MT2(+)
Figure 10. Exponential Static dv/dt versus
Gate−MT1 Resistance, MT2(−)
800
GATE OPEN
600
STATIC dv/dt (V/
m
s)
STATIC dv/dt (V/
m
s)
T
J
= 100°C
400
110°C
125°C
200
2000
1600
T
J
= 100°C
1200
110°C
800
125°C
GATE OPEN
400
0
400
500
600
700
800
400
500
600
700
800
V
PK
, PEAK VOLTAGE (VOLTS)
V
PK
, PEAK VOLTAGE (VOLTS)
0
Figure 11. Exponential Static dv/dt versus
Peak Voltage, MT2(+)
Figure 12. Exponential Static dv/dt versus
Peak Voltage, MT2(−)
http://onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
