VS-VSKDS403/100
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Vishay Semiconductors
AAP Gen 7 (TO-240AA)
Power Modules Schottky Rectifier, 200 A
FEATURES
• 175 °C T
J
operation
• Low forward voltage drop
• High frequency operation
• Low thermal resistance
• UL approved file E78996
• Designed and qualified for industrial level
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
AAP Gen 7 (TO-240AA)
BENEFITS
PRIMARY CHARACTERISTICS
I
F(AV)
V
R
Package
Circuit configuration
200 A
100 V
AAP Gen 7 (TO-240AA)
Two diodes doubler circuit
• Excellent thermal performances obtained by the usage of
exposed direct bonded copper substrate
• High surge capability
• Easy mounting on heatsink
ELECTRICAL DESCRIPTION / APPLICATIONS
The VS-VSKDS403.. Schottky rectifier doubler module has
been optimized for low reverse leakage at high temperature.
The proprietary barrier technology allows for reliable
operation up to 175 °C junction temperature.
Typical applications are in high current switching power
supplies, plating power supplies, UPS systems, converters,
freewheeling diodes, welding, and reverse battery
protection.
MECHANICAL DESCRIPTION
The AAP Gen 7, new generation of ADD-A-PAK module,
combines the excellent thermal performances obtained by
the usage of exposed direct bonded copper substrate, with
advanced compact simple package solution and simplified
internal structure with minimized number of interfaces.
MAJOR RATINGS AND CHARACTERISTICS
SYMBOL
I
F(AV)
V
RRM
I
FSM
V
F
T
J
t
p
= 5 μs sine
100 A
pk
, T
J
= 125 °C
Range
CHARACTERISTICS
Rectangular waveform
VALUES
200
100
23 000
0.66
-55 to +175
UNITS
A
V
A
V
°C
VOLTAGE RATINGS
PARAMETER
Maximum DC reverse voltage
Maximum working peak reverse voltage
SYMBOL
V
R
V
RWM
VS-VSKDS403/100
100
UNITS
V
Revision: 03-May-17
Document Number: 94642
1
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
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VS-VSKDS403/100
www.vishay.com
Vishay Semiconductors
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Maximum average forward current
Maximum peak one cycle
non-repetitive surge current
Non-repetitive avalanche energy
Repetitive avalanche current
SYMBOL
I
F(AV)
I
FSM
10 ms sine or 6 ms rect. pulse
E
AS
I
AR
T
J
= 25 °C, I
AS
= 5.5 A, L = 1 mH
Current decaying linearly to zero in 1 μs
Frequency limited by T
J
maximum V
A
= 1.5 x V
R
typical
TEST CONDITIONS
50 % duty cycle at T
C
= 104 °C, rectangular waveform
5 µs sine or 3 µs rect. pulse
Following any rated
load condition and with
rated V
RRM
applied
VALUES
200
23 000
2600
15
1
mJ
A
A
UNITS
ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
200 A
Maximum forward voltage drop
V
FM
400 A
200 A
400 A
Maximum reverse leakage current
Maximum junction capacitance
Typical series inductance
Maximum voltage rate of change
Maximum RMS insulation voltage
I
RM
C
T
L
S
dV/dt
V
INS
T
J
= 25 °C
T
J
= 125 °C
TEST CONDITIONS
T
J
= 25 °C
T
J
= 125 °C
V
R
= Rated V
R
VALUES
0.99
1.3
0.83
1.09
6
120
5500
5.0
10 000
3000 (1 min)
3600 (1 s)
mA
pF
nH
V/µs
V
V
UNITS
V
R
= 5 V
DC
(test signal range 100 kHz to 1 MHz), 25 °C
Measured lead to lead 5 mm from package body
Rated V
R
50 Hz
THERMAL - MECHANICAL SPECIFICATIONS
PARAMETER
Maximum junction and storage
temperature range
Maximum thermal resistance,
junction to case per leg
Typical thermal resistance,
case to heatsink per module
Approximate weight
to heatsink
Mounting torque ± 10 %
busbar
Case style
A mounting compound is recommended and the torque
should be rechecked after a period of 3 h to allow for the
spread of the compound.
JEDEC
®
SYMBOL
T
J
, T
Stg
R
thJC
R
thCS
DC operation
TEST CONDITIONS
VALUES
-55 to +175
0.32
°C/W
0.1
75
2.7
4
Nm
3
TO-240AA compatible
g
oz.
UNITS
°C
Revision: 03-May-17
Document Number: 94642
2
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-VSKDS403/100
www.vishay.com
Vishay Semiconductors
10000
1000
100
10
1
0.1
25 °C
175 °C
150 °C
125 °C
100 °C
75 °C
50 °C
I
F
- Instantaneous Forward Current
(A)
1000
100
T
J
= 175 °C
10
T
J
= 25 °C
I
R
- Reverse Current (mA)
0.01
0.001
T
J
= 125 °C
1
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
20
40
60
80
100
V
F
-
Forward Voltage Drop
(V)
Fig. 1 - Maximum Forward Voltage Drop Characteristics
V
R
- Reverse Voltage (V)
Fig. 2 - Typical Values of Reverse Current vs. Reverse Voltage
10 000
C
T
- Junction Capacitance (pF)
T
J
= 25 °C
1000
0
10
20
30
40
50
60
70
80
90 100
V
R
- Reverse Voltage (V)
Fig. 3 - Typical Junction Capacitance vs. Reverse Voltage
1
Z
thJC
- Thermal Impedance
Junction to Case (°C/W)
0.1
0.75
0.50
0.33
0.25
0.2
DC
0.01
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t
1
- Rectangular Pulse Duration (s)
Fig. 4 - Maximum Thermal Impedance Z
thJC
Characteristics
Revision: 03-May-17
Document Number: 94642
3
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-VSKDS403/100
www.vishay.com
Vishay Semiconductors
300
250
200
150
100
50
0
D = 0.20
D = 0.25
D = 0.33
D = 0.50
D = 0.75
DC
RMS limit
180
Allowable Case Temperature (°C)
160
140
120
100
80
60
40
20
0
0
100
200
300
400
500
I
F(AV)
- Average Forward Current
(A)
Square
wave (D = 0.50)
80 % rated V
R
applied
DC
see
note (1)
0
50
100
150
200
250
300
Average Power Loss (W)
I
F(AV)
- Average Forward Current (A)
Fig. 6 - Forward Power Loss Characteristics
Fig. 5 - Maximum Allowable Case Temperature vs.
Average Forward Current
I
FSM
- Non-Repetitive
Surge
Current
(A)
100 000
At any rated load condition
and with rated V
RRM
applied
following
surge
10 000
1000
10
100
1000
10 000
t
p
-
Square
Wave Pulse Duration (μs)
Fig. 7 - Maximum Non-Repetitive Surge Current
L
High-speed
switch
Freewheel
diode
40HFL40S02
+
V
d
= 25
V
D.U.T.
IRFP460
R
g
= 25
Ω
Current
monitor
Fig. 8 - Unclamped Inductive Test Circuit
Note
(1)
Formula used: T = T - (Pd + Pd
C
J
REV
) x R
thJC
;
Pd = forward power loss = I
F(AV)
x V
FM
at (I
F(AV)
/D) (see fig. 6);
Pd
REV
= inverse power loss = V
R1
x I
R
(1 - D); I
R
at V
R1
= 80 % rated V
R
Revision: 03-May-17
Document Number: 94642
4
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-VSKDS403/100
www.vishay.com
ORDERING INFORMATION TABLE
Vishay Semiconductors
Device code
VS-VS KD
1
2
S
3
40
4
3
5
/
100
6
1
2
3
4
5
6
-
-
-
-
-
-
VS-VS = Vishay Semiconductors product
Circuit configuration:
KD = ADD-A-PAK - 2 diodes doubler circuit
S = Schottky diode
Average rating (x 10)
Product silicon identification
Voltage rating (100 = 100 V)
CIRCUIT CONFIGURATION
(1)
~
(2)
+
(3)
-
LINKS TO RELATED DOCUMENTS
Dimensions
www.vishay.com/doc?95369
Revision: 03-May-17
Document Number: 94642
5
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000