Preliminary data
SPD02N60
SPU02N60
SIPMOS
®
Power Transistor
•
N-Channel
•
Enhancement mode
•
Avalanche rated
Pin 1
G
Type
SPD02N60
SPU02N60
Pin 2
D
Pin 3
S
V
DS
I
D
600 V 2 A
R
DS(on)
@ V
GS
Package
V
GS
= 10 V P-TO252
5.5
Ω
P-TO251
Ordering Code
Q67040-S4133
Q67040-S4127-A2
Maximum Ratings,
at
T
j = 25 °C, unless otherwise specified
Symbol
Parameter
Continuous drain current
Value
2
1.3
8
135
Unit
A
I
D
T
C
= 25 °C
T
C
= 100 °C
Pulsed drain current
I
Dpulse
E
AS
T
C
= 25 °C
Avalanche energy, single pulse
mJ
I
D
= 2 A,
V
DD
= 50 V,
R
GS
= 25
Ω,
T
j
= 25 °C
Gate source voltage
Power dissipation
V
GS
P
tot
T
j
T
stg
±20
55
-55 ... +150
-55 ... +150
55/150/56
V
W
°C
T
C
= 25 °C
Operating temperature
Storage temperature
IEC climatic category; DIN IEC 68-1
Semiconductor Group
1
10 / 1998
Preliminary data
SPD02N60
SPU02N60
Electrical Characteristics
Parameter
at
Tj
= 25 °C, unless otherwise specified
Thermal Characteristics
Thermal resistance, junction - case
Thermal resistance, junction - ambient
SMD version, device on PCB:
@ min. footprint
@ 6 cm
2
cooling area
1)
Symbol
min.
Values
typ.
max.
2.25
100
50
tbd
-
-
-
K/W
Unit
R
thJC
R
thJA
R
thJA
-
-
-
-
Static Characteristics
Drain- source breakdown voltage
V
(BR)DSS
V
GS(th)
I
DSS
600
2.1
-
3
-
4
V
V
GS
= 0 V,
I
D
= 0.25 mA
Gate threshold voltage,
V
GS
=
V
DS
I
D
= 1 mA
Zero gate voltage drain current
µA
-
-
0.1
-
10
4.2
1
100
100
5.5
nA
Ω
V
DS
= 600 V,
V
GS
= 0 V,
T
j
= 25 °C
V
DS
= 600 V,
V
GS
= 0 V,
T
j
= 150 °C
Gate-source leakage current
I
GSS
R
DS(on)
-
-
V
GS
= 20 V,
V
DS
= 0 V
Drain-Source on-state resistance
V
GS
= 10 V,
I
D
= 1.3 A
1 Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6 cm2 (one layer, 70µm thick) copper area for drain
connection. PCB is vertical without blown air.
Semiconductor Group
2
10 / 1998
Preliminary data
Electrical Characteristics
Parameter
Symbol
Values
SPD02N60
SPU02N60
Unit
at
Tj
= 25 °C, unless otherwise specified
Dynamic Characteristics
Transconductance
min.
typ.
1.8
350
40
15
10
max.
-
460
60
22
15
ns
S
pF
g
fs
C
iss
C
oss
C
rss
t
d(on)
1
-
-
-
-
V
DS
≥2*
I
D
*
R
DS(on)max
,
I
D
= 1.3 A
Input capacitance
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Output capacitance
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Reverse transfer capacitance
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Turn-on delay time
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 1.5 A,
R
G
= 50
Ω
Rise time
t
r
-
25
40
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 1.5 A,
R
G
= 50
Ω
Turn-off delay time
t
d(off)
-
35
50
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 1.5 A,
R
G
= 50
Ω
Fall time
t
f
-
25
35
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 1.5 A,
R
G
= 50
Ω
Semiconductor Group
3
10 / 1998
Preliminary data
SPD02N60
SPU02N60
Electrical Characteristics
Parameter
at
Tj
= 25 °C, unless otherwise specified
Reverse Diode
Inverse diode continuous forward current
Symbol
min.
Values
typ.
max.
Unit
I
S
I
SM
V
SD
t
rr
Q
rr
-
-
-
-
-
-
-
0.85
300
2.3
2
8
1.4
450
3.45
A
T
C
= 25 °C
Inverse diode direct current,pulsed
T
C
= 25 °C
Inverse diode forward voltage
V
ns
µC
V
GS
= 0 V,
I
F
= 4 A
Reverse recovery time
V
R
= 100 V,
I
F
=
I
S
, di
F
/dt = 100 A/µs
Reverse recovery charge
V
R
= 100 V,
I
F =
l
S
, di
F
/dt = 100 A/µs
Semiconductor Group
4
10 / 1998
Preliminary data
Power Dissipation
Drain current
SPD02N60
SPU02N60
P
tot
=
f
(T
C
)
SPD02N60
I
D
=
f
(T
C
)
parameter:
V
GS
≥
10 V
SPD02N60
60
W
2.4
A
50
45
2.0
1.8
1.6
P
tot
40
35
30
25
20
15
10
5
0
0
20
40
60
80
100
120
°C
I
D
1.4
1.2
1.0
0.8
0.6
0.4
0.2
160
0.0
0
20
40
60
80
100
120
°C
160
Safe operating area
T
C
Transient thermal impedance
T
j
I
D
=
f
(
V
DS
)
parameter :
D
= 0 ,
T
C
= 25 °C
10
1
SPD02N60
t
p = 30.0µs
Z
thJC
=
f(t
p
)
parameter :
D
=
t
p
/T
10
1
SPD02N60
K/W
A
100 µs
10
0
R
DS
(
on
)
Z
thJC
10
-1
D = 0.50
0.20
I
D
=
V
10
0
/I
D
DS
1 ms
10 ms
10
-1
DC
10
-2
single pulse
0.10
0.05
0.02
0.01
10
-2 0
10
10
1
10
2
V
10
3
10
-3 -7
10
10
-6
10
-5
10
-4
10
-3
10
-2
s
10
0
V
DS
Semiconductor Group
5
t
p
10 / 1998
FPGA/CPLD
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