F18 Series
•
Industry Standard Package and Circuits
•
Power Control Building Blocks
• Nine Circuits to Chose from
• UL Recognized E72445
AVAILABLE OPTIONS
ELECTRICAL SPECIFICATIONS
Description
Maximum DC Output Current (Tc = 85°C)
Maximum Voltage Drop @ Amps Peak
Operating Junction Temperature Range
Critical Rate of Rise of On-State Current @ TJ=125°C [A/µs]
Critical Rate of Rise of Off-State Voltage [V/µs]
Symbol
I
D
V
F
T
J
di/dt
dv/dt
27
25 A
1.55V @ 75 A
-40 - 125°C
100
1000
42
40 A
1.4V @ 120 A
-40 - 125°C
100
1000
57
55 A
1.4V @ 165 A
-40 - 125°C
100
1000
400 (120 VAC)
600 (240 VAC)
800 (280 VAC)
1200 (480 VAC)
1400 (530 VAC)
1600 (600 VAC)
1500
9350
150
3.0
0.5
5.0
0.25
2500
92
90 A
1.4V @ 270 A
-40 - 125°C
100
1000
107 (2)
105 A
1.65V @ 300 A
-40 - 125°C
100
1000
Repetitive Peak Reverse Voltage (AC Line Nominal) [Vpk]
V
RRM
Maximum Non-Repetitive Surge Current (1/2 Cycle, 60 Hz) [A]
Maximum I²T for Fusing (t=8.3ms) [A²sec]
Maximum Required Gate Current to Trigger @ 25°C [mA]
Maximum Required Gate Voltage to Trigger @ 25°C [V]
Average Gate Power [W]
Maximum Peak Reverse Gate Voltage [V]
Maximum Thermal Resistance, Junction to Ceramic Base per
Chip [°C/W]
Isolation Voltage [Vrms]
I
TSM
I
2
T
I
GT
V
GT
P
G(AV)
V
GM
R
JC
V
ISOL
400
670
150
3.0
0.5
5.0
0.4
2500
1000
4150
150
3.0
0.5
5.0
0.28
2500
1950
15800
150
3.0
0.5
5.0
0.14
2500
2250
25000
150
3.0
0.5
5.0
0.135
2500
GENERAL SPECIFICATIONS
Description
Weight (typical)
Torque Required
4.75 oz (135g)
Terminal Stud Screw : 30 in. lbs. Mounting Screws : 20 in. lbs.
GENERAL NOTES
1) All parameters at 25°C unless otherwise specified.
2) Available only in SD and SDK circuit configuration.
FPGA/CPLD
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