2N/PN/SST 4117,
4118, 4119
ULTRA-HIGH INPUT IMPEDANCE
N-CHANNEL JFET AMPLIFIER
FEATURES
LOW POWER
MINIMUM CIRCUIT LOADING
@ 25°C (unless otherwise noted)
Gate-Source or Gate-Drain Voltage
Gate-Current
Total Device Dissipation
(Derate 2mW/ºC above 25ºC)
Storage Temperature Range
Lead Temperature
(1/16” from case for 10 seconds)
300ºC
300mW
-55ºC to+150ºC
1
2
3
I
DSS
<600 µA (2N4117A)
I
GSS
<1 pA (2N4117A Series)
2N SERIES
TO-72
TOP VIEW
PN SERIES
TO-92
TOP VIEW
D
ABSOLUTE MAXIMUM RATINGS (NOTE 3)
-40V
50mA
SST SERIES
SOT-23
TOP VIEW
SOT-23
TOP VIEW
1
3
G
D
S
G
S
2
ELECTRICAL CHARACTERISTICS @ 25ºC (unless otherwise noted)
4117
SYMBOL
BV
GSS
V
GS(off)
I
DSS
CHARACTERISTIC
Gate-Source Breakdown
Voltage
Gate-Source Cutoff Voltage
Saturation Drain Current
(NOTE 2)
Gate Reverse Current
2N4117A, 2N4118A, 2N4119A
I
GSS
PN4117, PN4118, PN4119
SST4117, SST4118, SST4119
g
fs
g
os
C
iss
C
rss
Common-Source Forward
Transconductance
Common-Source Output
Conductance
Common-Source Input
Capacitance
(NOTE 4)
Common-Source Reverse
Transfer Capacitance
(NOTE 4)
--
--
70
--
--
--
-10
-25
450
3
3
1.5
--
--
80
--
--
--
-10
-25
650
5
3
1.5
--
--
100
--
--
--
-10
-25
700
µS
10
V
DS
=10V V
GS
=0
3
pF
1.5
f=1MHz
f=1kHz
pA
V
GS
=-10V V
DS
=0
nA
150ºC
MIN
-40
-0.6
0.03
--
--
MAX
--
-1.8
0.60
-1
-2.5
4118
MIN
-40
-1
0.08
--
--
MAX
--
-3
0.60
-1
-2.5
4119
MIN
-40
-2
0.20
--
--
MAX
--
-6
0.80
-1
-2.5
mA
pA
V
GS
=-20V V
DS
=0
nA
150ºC
UNITS
V
CONDITIONS
I
G
=-1µA
V
DS
=0
V
DS
=10V I
D
=1nA
V
DS
=10V V
GS
=0
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201135 11/30/2015 Rev#A9 ECN# 2N & SST 4117 4118 4119
STANDARD PACKAGE DIMENSIONS:
2N4117A, 2N4118A,
2N4119A
TO-72
Four Lead
PN4117, PN4118,
PN4119
TO-92
SST4117, SST4118,
SST4119
SOT-23
SOT-23
0.89
1.03
1
1.78
2.05
0.37
0.51
3
2.80
3.04
2
1.20
1.40
2.10
2.64
0.085
0.180
0.89
1.12
0.013
0.100
0.55
DIMENSIONS IN
MILLIMETERS
*Dimensions in inches
NOTES:
1. Due to symmetrical geometry, these units may be operated with source and drain leads interchanged.
2. This parameter is measured during a 2 ms interval 100 ms after power is applied. (Not a JEDEC condition.)
3. Absolute maximum ratings are limiting values above which serviceability may be impaired.
4. Not production tested, guaranteed by design.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use;
nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise
under any patent rights of Linear Integrated Systems.
5.
Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality
discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil
and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the
director of IC Development at Union Carbide, Co-Founder and Vice President of R&D at Intersil, and Founder/President of Micro
Power Systems.
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201135 11/30/2015 Rev#A9 ECN# 2N & SST 4117 4118 4119
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