2.5MHz Integrated Power Management IC with I
2
C
Compatible Interface
ISL80083
ISL80083 is an integrated mini Power Management IC
(mini-PMIC) for powering low-voltage microprocessor, or
applications using a single Li-Ion or Li-Polymer cell battery to
power multiple voltage rails. ISL80083 integrates a
high-efficiency 2.5MHz synchronous step-down converter, a
low-input low-dropout linear regulator, 33MHz oscillator, level
shift, and input supply select.
The 2.5MHz PWM switching frequency allows for the use of
very small external inductors and capacitors. The step-down
converter can enter skip mode under light load conditions to
further improve the efficiency and maximize the battery life.
For noise sensitive applications, it can also be programmed
through I
2
C interface to operate in forced PWM mode,
regardless of the load current condition. The I
2
C interface
supports on-the-fly control of the output voltage from 0.625V
to 2.225V at 25mV/step size for dynamic power saving. The
step-down converter can supply up to 800mA load current.
ISL80083 also provides a 300mA low dropout (LDO) regulator.
The input voltage range is from 2.6V to 5.5V allowing it to be
powered from one of the on-chip step-down converters or directly
from the battery. The default LDO output comes with factory
pre-set fixed output voltage options between 0.9V to 3.6V.
ISL80083 is available in a 2.11mm x 2.13mm 25 Ball CSP
package.
Features
• 800mA synchronous step-down converter and 300mA,
general-purpose LDO
• 400kb/s I
2
C-bus series interface transfers the control data
between the host controller and the ISL80083
• Fixed SMPS output voltage I
2
C programmability
- At 25mV/step. . . . . . . . . . . . . . . . . . . . . . 0.625V to 2.225V
• LDO output voltage I
2
C programmability
- At 50mV/step. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 3.6V
• 33MHz oscillator
• Level shift from 1.8V to 3V with enable
• Input select
• Switcher I
2
C programmable skip mode under light load or
forced fixed switching frequency PWM mode
Applications
• Power cable
100
90
EFFICIENCY (%)
80
70
60
50
40
0.0
1V - PFM
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD (3.3V
IN
, T
A =
+25°C)
May 15, 2013
FN7886.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80083
Pin Configuration
ISL80083
(25 BALL CSP 2.11 x 2.13mm)
TOP VIEW
1
2
3
4
5
A
-OSCOUT
+OSCOUT
OSCGND
CLK2P3IN
CLK2P3OUT
B
CFG2
LSRX
UART_EN
RESET
V3CLAMP
C
CFG2_CR
LSRX_CR
VOLDO
GNDLDO
GND
D
VIN_REMOTE
OSC_EN
SCLK
SDAT
1VAUX
E
VIN_HOST
VSELECT
PHASE
PGND
FB
Pin Descriptions
PIN NUMBER
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
PIN NAME
-OSCOUT
+OSCOUT
OSCGND
CLK2P3IN
CLK2P3OUT
CFG2
LSRX
UART_EN
RESET
V3CLAMP
CFG2_CR
LSRX_CR
VOLDO
DESCRIPTION
Negative terminal of the precision 33MHz oscillator differential output.
Positive terminal of the precision 33MHz oscillator differential output.
Isolated ground for the internal 33MHz oscillator.
2.3V input for the 33MHz oscillator. Connect a 220nF capacitor from CLK2P3OUT to OSCGND.
2.3V internal LDO output for the 33MHz oscillator. Connect CLK2P3IN to CLK2P3OUT along with a 220nF capacitor
for low noise performance.
This is the output of the level shifter from the CFG2_CR rail control signal shifting from 1.8V to 3V.
This is the output of the level shifter from the LSRX_CR rail control signal shifting from 1.8V to 3V.
Level shift of LSRX logic enable control. The output LSRX is in high Z state when UART_EN is pulled low. There is a
125kΩ pull-down resistor from this pin to GND.
This is a totem pole output to indicate a fault mode. The output is low if any of the fault is detected. The output is high
during normal operation.
This rail is a 3V LDO sourcing from VSELECT.
This is the input to the level shifter for the CONFIG2 rail control signal shifting from 3V to 1.8V.
This is the input to the level shifter from the LSRX rail control signal.
Output of the LDO.
2
FN7886.1
May 15, 2013
ISL80083
Pin Descriptions
(Continued)
PIN NUMBER
C4
C5
D1
D2
PIN NAME
GNDLDO
GND
VIN_REMOTE
OSC_EN
Power ground for LDO.
System ground for analog and digital circuitry.
Input voltage secondary for cases where VIN_HOST is valid, VIN_REMOTE is held off IC. If there is 2.6V present and VIN host
is not valid, then the pass MOSFET turns on. If this voltage is greater than 4.5V, then its pass MOSFET turn off.
Oscillator control pin. Connect to logic high will allow all outputs to operate normally and SMPS in PWM. Connecting
to logic low will disable the 33MHz oscillator, 1VAUX, and allow the SMPS to operate in high light load efficiency PFM.
There is a 125kΩ pull-up resistor from this pin to 1.8V.
I
2
C interface clock pin.
I
2
C interface data pin.
This rail is a low impedance pass PFET switch sourcing from switcher’s output thru the VFB pin.
Input voltage primary for the IC. If there is 2.6V present, then the pass MOSFET turns on. If this voltage is greater than 4.5V,
then its pass MOSFET turn off.
Input voltage for buck converter switcher, V3CLAMP, LDO, and it also serves as the power supply pin for the whole internal
digital/analog circuits.
Switching node for DC to DC converter; connect to one terminal of the inductor.
Power ground for switcher.
Feedback pin for switcher; connect external voltage divider resistors between switcher output, this pin and ground. For
fixed output versions, connect this pin directly to the switcher output.
DESCRIPTION
D3
D4
D5
E1
E2
E3
E4
E5
SCLK
SDAT
1VAUX
VIN_HOST
VSELECT
PHASE
PGND
FB
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL80083IIZ-T
ISL80083IIZ-TK
ISL80083IIZ-TS
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and
SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL80083.
For more information on MSL please see Tech Brief
TB363.
PART
MARKING
80083
80083
80083
FB
(V)
Adj
Adj
Adj
SLV
LDO
(V)
3.3
3.3
3.3
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
PACKAGE
Tape & Reel
(Pb-free)
25 Ball WLCSP
25 Ball WLCSP
25 Ball WLCSP
PKG.
DWG. #
W5x5.25B
W5x5.25B
W5x5.25B
3
FN7886.1
May 15, 2013
ISL80083
Block Diagram
VIN REMOTE
REMOTE
Q1
Q2
VSELECT
C1
10µF
VIN HOST
HOST
SELECTOR
LOGIC
2.5V TO 4.5V
PASS RANGE
PREFER “HOST”
INPUT
V3CLAMP
5k
Ω
5k
Ω
3V
CLAMP
OUT
Q3
V3CLAMP
15mA
C2
1µF
Q4
FAULT
VIN UV
OVP/
UVP
OCP
OTP
LDO OV
LDO UV
LDO
BUCK
CONTROL
VOLDO
LDOGND
PHASE
PGND
L1
1µH
C3
1µF
1.0V
C4
10µF
1.8V
SCLK
I
2
C
SSTIME
BUCK
VOUT
LDO VOUT
PWM/PFM
SDAT
Q5
Q6
LDO
GND
RESET
1.8V
1V AUX
Q7
FB
1V AUX
OSC_EN
CLK2P3IN
C6
220nF
OSCGND
500mA
C5
10µF
CFG2
CFG2_CR
LSRX_CR
LSRX
UART_EN
LEVEL
SHIFT
3V TO 1.8V
(LSRX
HI-Z OUT
DISABLE)
125k
Ω
125k
Ω
CONTROL
AGND
OSC
33MHz
OSC
LDO
+OSCOUT
TABLE 1. TYPICAL APPLICATION PART LIST
PARTS
L1
C1, C4,
C5
C2, C3
C6
DESCRIPTION
Inductor
Input and output
capacitor
Output capacitor
Bias Capacitor
MANUFACTURER
TDK
Murata
Murata
Various
PART NUMBER
VSF302512T-1R0
GRM21BR60J106KE19L
GRM185R60J105KE26D
GRM185R60J224KE26D
SPECIFICATIONS
1.0µH/1.8A/33mΩ
10µF/6.3V
1µF/6.3V
220nF/6.3V
SIZE
3.0mmx2.5mmx1.2mm
0402
0201
0201
4
-OSCOUT
CLK2P3OUT
AGND
OSCGND
FN7886.1
May 15, 2013
ISL80083
Absolute Maximum Ratings
(Refer to ground)
VIN_HOST, VIN_REMOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3V (DC) to 22V (DC)
VSELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3V (DC) to 6.5V (DC) or 7V (20ms)
PHASE. . . . . . . . . . . . . . . . . . . . .-1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
V3PCLAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
AGND, OSCGND, PGND, GNDLDO . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
1VAUX, CFG2, CFG2_CR, LSRX, LSRX_CR . . . . . . . . . . . . . . . -0.3V to 3.6V
RESET, SDAT, SCLK, UART_EN, VOLDO . . . . . . . . . . . . . . . . . . -0.3V to 3.6V
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.9V
ESD Ratings
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . . 1kV
Latch Up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
CSP Package (Notes 4, 5) . . . . . . . . . . . . . .
70
0.9
Maximum Junction Temperature Range . . . . . . . . . . . . . .-40°C to +150°C
Recommended Junction Temperature Range . . . . . . . . . . 0°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN_HOST, VIN_REMOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 20V
SMPS Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 800mA
LDO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 300mA
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5. For
θ
JC
, the “case temp” location is taken at the package top center.
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN_HOST or VIN_REMOTE = 3.3V. For LDO, VSELECT = VOLDO + 0.5V to
5.5V, L1 = 1.0µH, C1 = C4 = C5 = 10µF, C2 = C3 = C6 = 1µF, I
OUT
= 0A for SMPS and LDO (see Figure 1 for more details). Boldface limits apply across
the operating temperature range, -40°C to +85°C.
PARAMETER
VIN_HOST or VIN_REMOTE Voltage
Range
VSELECT Undervoltage Lockout
Threshold
Quiescent Supply Current on VSELECT
Thermal Shutdown
Thermal Shutdown Hysteresis
V
UVLO
Rising, I
OUT
= 0A for both SMPS and LDO
Falling
I
VSELECT
All outputs no loading
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
2.7
2.40
2.30
2.56
2.46
150
155
30
TYP
MAX
(Note 6)
20
2.62
2.57
500
UNIT
V
V
V
µA
°C
°C
Electrical Specifications
INPUT SELECTOR
VIN_HOST P-Channel MOSFET
ON-resistance
VIN_REMOTE P-Channel MOSFET ON-
resistance
Minimum Pass Range Voltage
Maximum Pass Range Voltage
Q1
Q2
V
IN_MIN
V
IN_Max
VSELECT = 3.3V, I
O
= 200mA
VSELECT = 3.3V, I
O
= 200mA
0.20
0.20
2.2
4.5
2.7
5.52
Ω
Ω
V
V
SMPS
Output Start Up Voltage
Line Regulation
P-Channel MOSFET ON-resistance
N-Channel MOSFET ON-resistance
P-Channel MOSFET Peak Current Limit
PWM Switching Frequency
SW Minimum ON-time
Q5
Q6
I
PK
f
S
f
OSC
/13
V
FB
= 2V
VSELECT = 3.3V, PWM
VSELECT = V
O
+ 0.5V to 5.5V (minimal 2.5V)
VSELECT = 3.3V, I
O
= 200mA
VSELECT = 3.3V, I
O
= 200mA
1
0.950
1.000
0.1
0.14
0.05
1.4
2.5
70
0.18
0.08
1.7
1.050
V
%/V
Ω
Ω
A
MHz
ns
5
FN7886.1
May 15, 2013
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