Intel® NM10 Family Express Chipset
Datasheet
December 2009
Document Number: 322896-001
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Datasheet
Contents
1
Introduction
............................................................................................................ 30
1.1
1.2
1.3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
3
3.1
3.2
3.3
4
5
Intel NM10 Family Express Chipset Feature Support ............................................... 31
Content Layout ................................................................................................. 34
Functions and capabilities ................................................................................... 36
Direct Media Interface (DMI) to Host Controller ..................................................... 45
PCI Express* .................................................................................................... 45
Platform LAN Connect Interface........................................................................... 45
EEPROM Interface ............................................................................................. 46
Firmware Hub Interface...................................................................................... 46
PCI Interface .................................................................................................... 47
Serial ATA Interface........................................................................................... 49
LPC Interface .................................................................................................... 50
Interrupt Interface ............................................................................................ 50
USB Interface ................................................................................................... 51
Power Management Interface.............................................................................. 52
Processor Interface............................................................................................ 54
SMBus Interface................................................................................................ 56
System Management Interface ............................................................................ 56
Real Time Clock Interface ................................................................................... 56
Other Clocks ..................................................................................................... 57
Miscellaneous Signals......................................................................................... 57
Intel HD Audio Link............................................................................................ 58
Serial Peripheral Interface (SPI) .......................................................................... 59
General Purpose I/O Signals ............................................................................... 59
Power and Ground ............................................................................................. 60
Pin Straps ........................................................................................................ 61
2.22.1 Functional Straps ................................................................................... 61
2.22.2 External RTC Circuitry ............................................................................. 63
Device and Revision ID Table .............................................................................. 64
Integrated Pull-Ups and Pull-Downs ..................................................................... 65
Output and I/O Signals Planes and States............................................................. 66
Power Planes for Input Signals ............................................................................ 71
Signal Description....................................................................................................
43
Pin States
................................................................................................................ 65
Chipset and System Clock Domains.........................................................................
74
Functional Description
............................................................................................. 76
5.1
PCI-to-PCI Bridge (D30:F0) ................................................................................ 76
5.1.1 PCI Bus Interface ................................................................................... 76
5.1.2 PCI Bridge As an Initiator ........................................................................ 76
5.1.3 Parity Error Detection and Generation ....................................................... 78
5.1.4 PCIRST# ............................................................................................... 79
5.1.5 Peer Cycles............................................................................................ 79
5.1.6 PCI-to-PCI Bridge Model .......................................................................... 80
5.1.7 IDSEL to Device Number Mapping............................................................. 80
5.1.8 Standard PCI Bus Configuration Mechanism ............................................... 80
Datasheet
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5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
PCI Express* Root Ports (D28:F0,F1,F2,F3)...........................................................81
5.2.1 Interrupt Generation ...............................................................................81
5.2.2 Power Management.................................................................................82
5.2.3 SERR# Generation ..................................................................................83
5.2.4 Hot-Plug ................................................................................................84
LAN Controller (B1:D8:F0) ..................................................................................86
5.3.1 LAN Controller PCI Bus Interface...............................................................86
5.3.2 Serial EEPROM Interface ..........................................................................91
5.3.3 CSMA/CD Unit ........................................................................................91
5.3.4 Media Management Interface ...................................................................92
5.3.5 TCO Functionality ...................................................................................92
Alert Standard Format (ASF) ...............................................................................94
5.4.1 ASF Management Solution Features/Capabilities .........................................95
5.4.2 ASF Hardware Support ............................................................................96
5.4.3 ASF Software Support .............................................................................97
LPC Bridge (w/ System and Management Functions) (D31:F0) .................................98
5.5.1 LPC Interface .........................................................................................98
5.5.2 SERR# Generation ................................................................................ 103
DMA Operation (D31:F0) .................................................................................. 104
5.6.1 Channel Priority.................................................................................... 105
5.6.2 Address Compatibility Mode ................................................................... 105
5.6.3 Summary of DMA Transfer Sizes ............................................................. 106
5.6.4 Autoinitialize ........................................................................................ 106
5.6.5 Software Commands ............................................................................. 107
LPC DMA ........................................................................................................ 107
5.7.1 Asserting DMA Requests ........................................................................ 107
5.7.2 Abandoning DMA Requests..................................................................... 108
5.7.3 General Flow of DMA Transfers ............................................................... 108
5.7.4 Terminal Count..................................................................................... 109
5.7.5 Verify Mode ......................................................................................... 109
5.7.6 DMA Request Deassertion ...................................................................... 109
5.7.7 SYNC Field / LDRQ# Rules ..................................................................... 110
8254 Timers (D31:F0) ...................................................................................... 111
5.8.1 Timer Programming .............................................................................. 112
5.8.2 Reading from the Interval Timer ............................................................. 113
8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 114
5.9.1 Interrupt Handling ................................................................................ 116
5.9.2 Initialization Command Words (ICWx) ..................................................... 117
5.9.3 Operation Command Words (OCW) ......................................................... 118
5.9.4 Modes of Operation ............................................................................... 118
5.9.5 Masking Interrupts................................................................................ 121
5.9.6 Steering PCI Interrupts.......................................................................... 121
Advanced Programmable Interrupt Controller (APIC) (D31:F0)............................... 122
5.10.1 Interrupt Handling ................................................................................ 122
5.10.2 Interrupt Mapping................................................................................. 122
5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 123
5.10.4 Front Side Bus Interrupt Delivery ............................................................ 124
Serial Interrupt (D31:F0) .................................................................................. 126
5.11.1 Start Frame ......................................................................................... 126
5.11.2 Data Frames ........................................................................................ 126
5.11.3 Stop Frame.......................................................................................... 127
5.11.4 Specific Interrupts Not Supported via SERIRQ........................................... 127
5.11.5 Data Frame Format............................................................................... 127
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Datasheet
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
Real Time Clock (D31:F0)................................................................................. 129
5.12.1 Update Cycles ...................................................................................... 129
5.12.2 Interrupts ........................................................................................... 130
5.12.3 Lockable RAM Ranges ........................................................................... 130
5.12.4 Century Rollover .................................................................................. 130
5.12.5 Clearing Battery-Backed RTC RAM .......................................................... 131
Processor Interface (D31:F0) ............................................................................ 132
5.13.1 Processor Interface Signals .................................................................... 133
5.13.2 Dual-Processor Issues (Nettop Only) ....................................................... 135
Power Management (D31:F0)............................................................................ 136
5.14.1 Features ............................................................................................. 136
5.14.2 Chipset and System Power States........................................................... 137
5.14.3 System Power Planes ............................................................................ 139
5.14.4 SMI#/SCI Generation ........................................................................... 140
5.14.5 Dynamic Processor Clock Control ............................................................ 142
5.14.6 Dynamic PCI Clock Control (Netbook Only) .............................................. 145
5.14.7 Sleep States ........................................................................................ 147
5.14.8 Thermal Management ........................................................................... 150
5.14.9 Event Input Signals and Their Usage ....................................................... 152
5.14.10ALT Access Mode .................................................................................. 155
5.14.11System Power Supplies, Planes, and Signals ............................................ 158
5.14.12Clock Generators.................................................................................. 161
5.14.13Legacy Power Management Theory of Operation ....................................... 162
System Management (D31:F0).......................................................................... 163
5.15.1 Theory of Operation.............................................................................. 163
5.15.2 Heartbeat and Event Reporting via SMBus ............................................... 164
SATA Host Controller (D31:F2).......................................................................... 168
5.16.1 Theory of Operation.............................................................................. 170
5.16.2 SATA Swap Bay Support........................................................................ 171
5.16.3 Power Management Operation................................................................ 171
5.16.4 SATA LED............................................................................................ 173
5.16.5 AHCI Operation .................................................................................... 173
High Precision Event Timers .............................................................................. 174
5.17.1 Timer Accuracy .................................................................................... 174
5.17.2 Interrupt Mapping ................................................................................ 175
5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 175
5.17.4 Enabling the Timers .............................................................................. 176
5.17.5 Interrupt Levels ................................................................................... 176
5.17.6 Handling Interrupts .............................................................................. 176
5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 177
USB UHCI Host Controllers (D29:F0, F1, F2, and F3)............................................ 177
5.18.1 Data Structures in Main Memory............................................................. 177
5.18.2 Data Transfers to/from Main Memory ...................................................... 178
5.18.3 Data Encoding and Bit Stuffing ............................................................... 178
5.18.4 Bus Protocol ........................................................................................ 178
5.18.5 Packet Formats .................................................................................... 179
5.18.6 USB Interrupts..................................................................................... 179
5.18.7 USB Power Management ....................................................................... 182
5.18.8 USB Legacy Keyboard Operation............................................................. 182
USB EHCI Host Controller (D29:F7) ................................................................... 185
5.19.1 EHC Initialization.................................................................................. 185
5.19.2 Data Structures in Main Memory............................................................. 186
5.19.3 USB 2.0 Enhanced Host Controller DMA ................................................... 186
Datasheet
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