FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Current Mode PWM Controller
June 2011
FAN6921MR
Integrated Critical Mode PFC and Quasi-Resonant
Current Mode PWM Controller
Features
Integrated PFC and Flyback Controller
Critical Mode PFC Controller
Zero-Current Detection for PFC Stage
Quasi-Resonant Operation for PWM Stage
Internal Minimum t
OFF
8µs for QR PWM Stage
Internal 10ms Soft-Start for PWM
Brownout Protection
High / Low Line Over-Power Compensation
Auto-Recovery Over-Current Protection
Auto-Recovery Open-Loop Protection
Externally Latch Triggering (RT Pin)
Adjustable Over-Temperature Latched (RT Pin)
VDD Pin and Output Voltage OVP (Latched)
Internal Over-Temperature Shutdown (140°C)
Description
The highly integrated FAN6921MR combines Power
Factor Correction (PFC) controller and Quasi-Resonant
PWM controller. Integration provides cost effect design
and allows for fewer external components.
For PFC, FAN6921MR uses a controlled on-time
technique to provide a regulated DC output voltage and
to perform natural power factor correction. With an
innovative THD optimizer, FAN6921MR can reduce
input current distortion at zero-crossing duration to
improve THD performance.
For PWM, FAN6921MR provides several functions to
enhance the power system performance: valley
detection, green-mode operation, high / low line over
power compensation. FAN6921MR provides many
protection functions as well: secondary-side open-loop
and over-current with auto recovery protection, external
latch triggering, adjustable over-temperature protection
by RT pin and external NTC resistor, internal over-
temperature shutdown, V
DD
pin OVP, and DET pin over-
voltage for output OVP, and brown-in / out for AC input
voltage UVP.
The FAN6921MR controller is available in a 16-pin small
outline package (SOP).
Applications
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Ordering Information
Part Number
FAN6921MRMY
OLP
Mode
Recovery
Operating
Temperature Range
-40°C to +105°C
Package
16-Pin Small Outline Package (SOP)
Packing
Method
Tape & Reel
© 2009 Fairchild Semiconductor Corporation
FAN6921MR Rev. 1.0.2
www.fairchildsemi.com
FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Application Diagram
Figure 1. Typical Application
© 2009 Fairchild Semiconductor Corporation
FAN6921MR Rev. 1.0.2
www.fairchildsemi.com
2
FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN6921MR Rev. 1.0.2
www.fairchildsemi.com
3
FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Marking Information
Figure 3. Marking Diagram
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
1
Name
RANGE
Description
RANGE pin’s impedance changes according to VIN pin voltage level. When the input voltage
detected by VIN pin is lower than a threshold voltage, it sets to high impedance; whereas it sets
to low impedance if input voltage is high level.
Output pin of the error amplifier. It is a transconductance type error amplifier for PFC output
voltage feedback. Proprietary multi-vector current is built-in to this amplifier. Therefore the
compensation for PFC voltage feedback loop allows a simple compensation circuit between this
pin and GND.
Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage
divider and provides PFC output over- and under-voltage protections.
Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting
protection. When the sensed voltage across the PFC current sensing resistor reaches the internal
threshold (0.82V typical), the PFC switch is turned off to activate cycle-by-cycle current limiting.
2
COMP
3
4
INV
CSPFC
5
Input to the comparator of the PWM over-current protection and performs PWM current-mode
control with FB pin voltage. A resistor is used to sense the switching current of PWM switch and
CSPWM the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, current-
mode control, and high / low line over-power compensation according to DET pin source current
during PWM t
ON
time.
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN6921MR Rev. 1.0.2
www.fairchildsemi.com
4
FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller
Pin Definitions
(Continued)
Pin #
6
7
8
9
Name
OPFC
VDD
OPWM
GND
Description
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage
is 15.5V.
Power supply. The threshold voltage for startup and turn-off is 18V and 7.5V, respectively. The
startup current is less than 30µA and the operating current is lower than 10mA.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
gate output voltage is 17.5V.
The power ground and signal ground.
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
Producing an offset voltage to compensate the threshold voltage of PWM current limit for
providing over-power compensation. The offset is generated in accordance with the input
voltage when PWM switch is on.
Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on PWM switch.
Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
OVP and this flat voltage is higher than 2.5V, the controller enters latch mode and stops all
PFC and PWM switching operation.
Feedback voltage pin. This pin is used to receive output voltage level signal to determine PWM
gate duty for regulating output voltage. The FB pin voltage can also activate open-loop, over-load
protection, and output-short circuit protection if the FB pin voltage is higher than a threshold of
around 4.2V for more than 50ms.The input impedance of this pin is a 5kΩequivalent resistance. A
1/3 attenuator is connected between the FB pin and the input of the CSPWM/FB comparator.
Adjustable over-temperature protection and external latch triggering. A constant current is flowed
out of the RT pin. When RT pin voltage is lower than 0.8V (typical), latch mode protection is
activated and stops all PFC and PWM switching operation until the AC plug is removed.
Line-voltage detection for brown-in / out protections. This pin can receive the AC input voltage
level through a voltage divider. The voltage level of the VIN pin is not only used to control
RANGE pin’s status, but it can also perform brown-in / out protection for AC input voltage UVP.
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching
cycle. When the ZCD pin voltage is pulled to under 0.2V (typical), it disables the PFC stage and
the controller stops PFC switching. This can be realized with an external circuit if disabling the
PFC stage is desired.
No connection
High-voltage startup. HV pin is connected to the AC line voltage through a resistor
(100kΩtypical) for providing a high charging current to V
DD
capacitor.
10
DET
11
FB
12
RT
13
VIN
14
ZCD
15
16
NC
HV
© 2009 Fairchild Semiconductor Corporation
FAN6921MR Rev. 1.0.2
www.fairchildsemi.com
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