UNISONIC TECHNOLOGIES CO., LTD
UF830Z
4.5A, 500V, 1.5Ω, N-CHANNEL
POWER MOSFET
DESCRIPTION
The N-Channel enhancement mode silicon gate power MOSFET is
designed for high voltage, high speed power switching applications, such as
switching regulators, switching converters, solenoid, motor drivers and
related drivers.
1
Power MOSFET
TO-220F
FEATURES
* V
DS
= 500V
* I
D
= 4.5A
* R
DS(ON)
=1.5Ω
* Single Pulse Avalanche Energy Rated
* Rugged- SOA is Power Dissipation Limited
* Fast Switching Speeds
* Linear Transfer Characteristics
* High Input Impedance
* ESD Protected
SYMBOL
2.Drain
1.Gate
3.Source
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
UF830ZL-TF3-T
UF830ZG-TF3-T
Package
TO-220F
Pin Assignment
1
2
3
G
D
S
Packing
Tube
www.unisonic.com.tw
Copyright © 2011 Unisonic Technologies Co., Ltd
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ABSOLUTE MAXIMUM RATINGS
(
Ta = 25°C, Unless Otherwise Specified.)
Power MOSFET
PARAMETER
SYMBOL
RATINGS
UNIT
Drain to Source Voltage (T
J
=25°C ~125°C)
V
DS
500
V
Drain to Gate Voltage (R
GS
=20kΩ, T
J
=25°C ~125°C)
V
DGR
500
V
Gate to Source Voltage
V
GS
±30
V
Continuous
I
D
4.5
A
Drain Current
Pulsed
I
DM
18
A
Power Dissipation (T
C
= 25°C)
P
D
38
W
Single Pulse Avalanche Energy Rating (Note 2)
E
AS
300
mJ
Junction Temperature
T
J
+150
°C
Storage Temperature
T
STG
-55 ~ +150
°C
Note: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. V
DD
=50V, starting T
J
=25°C, L=25mH, R
G
=25Ω, peak I
AS
=4.5A
THERMAL DATA
PARAMETER
Junction to Ambient
Junction to Case
SYMBOL
θ
JA
θ
Jc
RATINGS
62.5
3.31
UNIT
°C/W
°C/W
ELECTRICAL SPECIFICATIONS
(Ta =25°C, unless otherwise specified.)
PARAMETER
Drain-Source Breakdown Voltage
Gate Threshold Voltage
On-State Drain Current (Note 1)
Drain-Source Leakage Current
SYMBOL
BV
DSS
V
GS(TH)
I
D(ON)
I
DSS
TEST CONDITIONS
I
D
=250μA, V
GS
=0V
V
GS
=V
DS
, I
D
=250μA
V
DS
>I
D(ON)
×R
DS(ON)MAX
, V
GS
=10V
V
DS
= Rated BV
DSS
, V
GS
=0V
V
DS
=0.8×Rated BV
DSS
V
GS
=0V, T
J
= 125°C
V
GS
=±30V
MIN
500
2.0
4.5
TYP MAX UNIT
V
4.0
V
A
25
μA
250
±800
1.3
4.2
10
15
33
16
22
3.5
11
600
100
20
1.5
17
23
53
23
32
μA
nA
Ω
S
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
Gate-Source Leakage Current
I
GSS
Static Drain-Source On-State Resistance
R
DS(ON)
I
D
=2.5A, V
GS
=10V
(Note 2)
Forward Transconductance (Note 1)
g
FS
V
DS
≥10V,
I
D
=2.7A
2.5
Turn-On Delay Time
t
D(ON)
Turn-On Rise Time
t
R
V
DD
=250V, I
D
≈4.5A
R
GS
=12Ω, R
L
=54Ω (Note 2)
Turn-Off Delay Time
t
D(OFF)
Turn-Off Fall Time
t
F
Total Gate Charge
Q
G
V
GS
=10V, I
D
=4.5A
V
DS
=0.8×Rated BV
DSS
Gate-Source Charge
Q
GS
I
G(REF)
=1.5mA (Note 3)
Gate-Drain Charge
Q
GD
Input Capacitance
C
ISS
V
DS
=25V, V
GS
=0V, f=1.0MHz
Output Capacitance
C
OSS
Reverse Transfer Capacitance
C
RSS
Note: 1. Pulse Test: Pulse width≤300μs, Duty Cycle≤2%.
2. MOSFET Switching Times are Essentially Independent of Operating Temperature.
3. Gate Charge is Essentially Independent of Operating Temperature.
UNISONIC TECHNOLOGIES CO., LTD
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UF830Z
INTERNAL PACKAGE INDUCTANCE
PARAMETER
SYMBOL
Internal Drain Inductance
Measured from the contact screw on tab to center of die
L
D
Measured from the drain lead(6mm from package) to center of die
Internal Source Inductance
Measured from the source lead(6mm from header) to source bond pad
L
S
Remark:
Modified MOSFET symbol showing the internal devices inductances as below.
Power MOSFET
MIN
TYP
3.5
4.5
7.5
MAX UNIT
nH
nH
nH
SOURCE TO DRAIN DIODE SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Source to Drain Diode Voltage
V
SD
T
J
=25°C, I
SD
=4.5A, V
GS
=0V
(Note 1)
Continuous Source to Drain Current
I
SD
Note 2
Pulse Source to Drain Current
I
SDM
Reverse Recovery Time
t
RR
T
J
=25°C, I
SD
=4.5A, dI/dt=100A/μs
180
Reverse Recovery Charge
Q
RR
T
J
=25°C, I
SD
=4.5A, dI/dt=100A/μs
0.96
NOTE : 1. Pulse Test: Pulse width≤300μs, Duty Cycle≤2%.
2. Modified MOSFET symbol showing the integral reverse P-N junction diode as below.
D
TYP
MAX UNIT
1.6
5.5
18
760
4.3
V
A
A
ns
μC
350
2.2
G
S
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TEST CIRCUITS AND WAVEFORMS
V
DS
Power MOSFET
L
VARY tp TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
0V
t
p
+
V
DD
-
R
G
I
AS
0.01Ω
FIG 1. Unclamped Energy Test Circuit
FIG 2. Unclamped Energy Waveforms
R
L
+
V
DD
-
DUT
R
G
V
GS
FIG 3. Switching Time Test Circuit
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TEST CIRCUITS AND WAVEFORMS (Cont.)
t
ON
t
DLY(ON)
t
R
V
DS
90%
t
OFF
t
DLY(OFF)
t
F
Power MOSFET
90%
10%
90%
0
10%
V
GS
0
10%
50%
PULSE WIDTH
50%
FIG 4. Resistive Switching Waveforms
FIG 5. Gate Charge Test Circuit
FIG 6. Gate Charge Waveforms
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www.unisonic.com.tw
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QW-R502-612.A
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