Preliminary
Datasheet
TBB1002
Twin Built in Biasing Circuit MOS FET IC
VHF/UHF RF Amplifier
Features
•
•
•
•
R07DS0313EJ1000
(Previous: REJ03G0841-0900)
Rev.10.00
Mar 28, 2011
Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
Suitable for World Standard Tuner RF amplifier.
Very useful for total tuner cost reduction.
Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200 V at C = 200 pF,
Rs = 0 conditions.
•
Provide mini mold packages; CMPAK-6
Outline
RENESAS Package code: PTSP0006JA-A
(Package name: CMPAK-6)
6
5
4
2
1
3
1. Gate-1(1)
2. Source
3. Drain(1)
4. Drain(2)
5. Gate-2
6. Gate-1(2)
Notes:
1. Marking is “BM”.
2. TBB1002 is individual type number of RENESAS TWIN BBFET.
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Gate2 to source voltage
Drain current
Channel power dissipation
Channel temperature
Storage temperature
Symbol
V
DS
V
G1S
V
G2S
I
D
Pch
*3
Tch
Tstg
Ratings
6
+6
-0
+6
-0
30
250
150
–55 to +150
Unit
V
V
V
mA
mW
°C
°C
Notes: 3. Value on the glass epoxy board (49mm
×
38mm
×
1mm).
R07DS0313EJ1000 Rev.10.00
Mar 28, 2011
Page 1 of 8
TBB1002
Preliminary
Electrical Characteristics
The below specification are applicable for UHF unit (FET1)
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Gate2 to source breakdown voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Gate2 to source cutoff voltage
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
Symbol
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
I
G1SS
I
G2SS
V
G1S(off)
V
G2S(off)
I
D(op)
|y
fs
|
Ciss
Coss
Crss
PG
NF
Min
6
+6
+6
—
—
0.5
0.5
13
21
1.4
1.0
—
16
—
Typ
—
—
—
—
—
0.75
0.75
17
26
1.8
1.4
0.02
21
1.7
Max
—
—
—
+100
+100
1.0
1.0
21
31
2.2
1.8
0.04
—
2.5
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
pF
dB
dB
Test conditions
I
D
= 200
μA,
V
G1S
= V
G2S
= 0
I
G1
= +10
μA,
V
G2S
= V
DS
= 0
I
G2
= +10
μA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V
I
D
= 100
μA
V
DS
= 5 V, V
G1S
= 5 V
I
D
= 100
μA
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 1 kHz
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 100 kΩ
f = 1 MHz
V
DS
= V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 900 MHz
Zi =S11*, Zo=S22*(:PG)
Zi =S11opt (:NF)
The below specification are applicable for VHF unit (FET2)
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Gate2 to source breakdown voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Gate2 to source cutoff voltage
Drain current
Forward transfer admittance
Symbol
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
I
G1SS
I
G2SS
V
G1S(off)
V
G2S(off)
I
D(op)
|y
fs
|
Min
6
+6
+6
—
—
0.5
0.5
14
20
Typ
—
—
—
—
—
0.75
0.75
18
25
Max
—
—
—
+100
+100
1.0
1.0
22
30
Unit
V
V
V
nA
nA
V
V
mA
mS
Test conditions
I
D
= 200
μA,
V
G1S
= V
G2S
= 0
I
G1
= +10
μA,
V
G2S
= V
DS
= 0
I
G2
= +10
μA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V
I
D
= 100
μA
V
DS
= 5 V, V
G1S
= 5 V
I
D
= 100
μA
V
DS
= 5V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 82 kΩ
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 82 kΩ
f = 1 kHz
V
DS
= 5 V, V
G1
= 5 V
V
G2S
=4 V, R
G
= 82 kΩ
f = 1 MHz
V
DS
= V
G1
= 5 V, V
G2S
= 4 V
R
G
= 82 kΩ, f = 200 MHz
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
Ciss
Coss
Crss
PG
NF
2.2
1.2
—
22
—
2.6
1.6
0.03
27
1.2
3.0
2.0
0.05
—
1.7
pF
pF
pF
dB
dB
R07DS0313EJ1000 Rev.10.00
Mar 28, 2011
Page 2 of 8
TBB1002
Preliminary
Test Circuits
•
DC Biasing Circuit for Operating Characteristic Items
(I
D(op)
, |yfs|, Ciss, Coss, Crss, NF, PG)
Measurment of FET1
Gate 2
V
G2
Open
Open
R
G
V
G1
Gate 1
Source
Drain
A
I
D
V
D
Measurment of FET2
V
G2
Gate 2
R
G
V
G1
Gate 1
Drain
A
I
D
V
D
Open
Source
Open
R07DS0313EJ1000 Rev.10.00
Mar 28, 2011
Page 3 of 8
TBB1002
•
Equivalent Circuit
No.1
Gate-1(1)
BBFET-(1)
No.2
Source
BBFET-(2)
No.5
Gate-2
No.6
Gate-1(2)
Preliminary
No.3
Drain(1)
No.4
Drain(2)
•
200 MHz Power Gain, Noise Figure Test Circuit
V
T
1000p
V
G2
1000p
V
T
1000p
47k
Input(50Ω)
L1
1000p
36p
1000p
47k
TWINBBFET
L2
1000p
47k
Output(50Ω)
10p max
1000p
1SV70
R
G
82k
RFC
1SV70
1000p
V
D
= V
G1
Unit :
Resistance (Ω)
Capacitance (F)
L1 :
φ1mm
Enameled
Copper
Wire,Inside
dia 10mm, 2Turns
L2 :
φ1mm
Enameled
Copper
Wire,Inside
dia 10mm, 2Turns
RFC
:
φ1mm
Enameled
Copper
Wire,Inside
dia 5mm, 2Turns
R07DS0313EJ1000 Rev.10.00
Mar 28, 2011
Page 4 of 8
TBB1002
Maximum Channel Power
Dissipation Curve
Channel Power Dissipation Pch* (mW)
400
Preliminary
Typical Output
Characteristics (FET1)
25
6
8
k
G
=
R
8
2
15
10
0
200
0
12
10
15
100
5
1
8
0k
0
50
100
150
200
0
1
2
3
4
k
Ω
k
Ω
300
Drain Current
I
D
(mA)
20
V
G2S
= 4 V
V
G1
= V
DS
Ω
k
Ω
0
k
Ω
Ω
5
Ambient
Temperature Ta
(°C)
* Value
on the glass epoxy
board
(49mm
×
38mm
×
1mm)
Drain to Source
Voltage V
DS
(V)
Forward Transfer
Admittance
vs.
Gate1
Voltage
(FET1)
Forward Transfer
Admittance
|y
fs
|
(mS)
50
V
G2S
=
5
V
V
DS
= 4 V
40
R
G
=
68 k
Ω
Drain Current
vs.
Gate1
Voltage
(FET1)
25
V
DS
=
5
V
R
G
=
120 k
Ω
4V
20
Drain Current
I
D
(mA)
15
3
V
30
100 k
Ω
10
2
V
20
150 k
Ω
5
V
G2S
=
1
V
10
0
1
2
3
4
5
0
1
2
3
4
5
Gate1
Voltage V
G1
(V)
Drain Current
vs.
Gate Resistance (FET1)
30
25
20
15
10
5
0
10
4
V
DS
=
5
V
V
G1
=
5
V
V
G2S
= 4 V
Gate1
Voltage V
G1
(V)
Input
Capacitance
vs.
Gate2 to Source
Voltage
(FET1)
Input
Capacitance Ciss (pF)
Drain Current
I
D
(mA)
3
2
V
DS
=
5
V
V
G1
=
5
V
R
G
=
100 kΩ
f =
1 MHz
0
1
2
3
4
1
20
50
100 200
500 1000
0
Gate Resistance R
G
(kΩ)
Gate2 to Source
Voltage V
G2S
(V)
R07DS0313EJ1000 Rev.10.00
Mar 28, 2011
Page 5 of 8
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