25AA320
32K 1.8V SPI
™
Bus Serial EEPROM
FEATURES
• SPI modes 0,0 and 1,1
• 3.0 MHz Clock Rate
• Single supply with Programming Operation down
to 1.8V
• Low Power CMOS Technology
- Max Write Current: 5.0 mA
- Read Current: 1.0 mA@ 5.5V 3 Mhz
- Standby Current: 1
µ
A typical
• 4096 x 8 Organization
• 32-Byte Page
• Sequential Read
• Self-timed ERASE and WRITE Cycles
• Block Write Protection
- Protect none, 1/4, 1/2, or all of Array
• Built-in Write Protection
- Power On/Off Data Protection Circuitry
- Write Enable Latch
- Write Protect Pin
• High Reliability
- Endurance: 1M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000V
• 8-pin PDIP/SOIC, 14-pin TSSOP
• Temperature ranges supported:
- Commercial (C):
0
°
C to +70
°
C
- Industrial (I)
-40
°
C to +85
°
C
PACKAGE TYPES
DIP/SOIC
CS
SO
WP
V
SS
TSSOP
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
V
SS
7
14 V
CC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
1
25AA320
25AA320
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
BLOCK DIAGRAM
Status
Register
HV Generator
EEPROM
I/O Control
Logic
Memory
Control
Logic
X
Dec
Page Latches
WP
SI
SO
CS
SCK
HOLD
Vcc
Vss
Sense Amp.
R/W Control
Y Decoder
Array
DESCRIPTION
The Microchip Technology Inc. 25AA320 is a 32K-bit
serial Electrically Erasable PROM (EEPROM). The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also, write
operations to the Status Register can be disabled via
the write protect pin (WP).
SPI is a trademark of Motorola.
©
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21157B-page 1
25AA320
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings
*
FIGURE 1-2: AC TEST CIRCUIT
Vcc
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
....... -0.6V to V
CC
+1.0V
Storage temperature ............................ -65
°
C to 150
°
C
Ambient temperature under bias.......... -65
°
C to 125
°
C
Soldering temperature of leads
(10 seconds) .................................................... +300
°
C
ESD protection on all pins..................................... 4 kV
*Notice:
Stresses above those listed under ‘Maximum ratings’
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended period of time may affect device reliability
2.25 K
SO
1.8 K
100 pF
1.2
AC Test Conditions
FIGURE 1-1:
Name
CS
SO
SI
SCK
WP
V
SS
V
CC
HOLD
NC
PIN FUNCTION TABLE
Function
AC Waveform:
V
LO
= 0.2V
V
HI
= Vcc - 0.2V
V
HI
= 4.0V
(Note 1)
(Note 2)
Chip Select Input
Serial Data Output
Serial Data Input
Serial Clock Input
Write Protect Pin
Ground
Supply Voltage
Hold Input
No Connect
Timing Measurement Reference Level
Input
0.5 V
CC
Output
0.5 V
CC
Note 1: For V
CC
≤
4.0V
2: For V
CC
> 4.0V
TABLE 1-1:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
V
CC
= +1.8V to 5.5V
Commercial (C): Tamb = 0
°
C to +70
°
C
Industrial (I):
Tamb =-40
°
C to +85
°
C
Parameter
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
Internal Capacitance
(all inputs and outputs)
Operating Current
Symbol
V
IH1
V
IH2
V
IL1
V
IL2
V
OL
V
OH
I
LI
I
LO
C
INT
Icc Write
Min
2.0
0.7 V
CC
-0.3
-0.3
—
V
CC
-0.5
-10
-10
—
—
—
—
—
—
Max
V
CC
+1
V
CC
+1
0.8
0.3 V
CC
0.4
—
10
10
7
Units
V
V
V
V
V
V
µ
A
µ
A
pF
Test Conditions
V
CC
≥
2.7V
V
CC
< 2.7V
V
CC
≥
2.7V
V
CC
< 2.7V
I
OL
=2.1 mA
I
OH
=-400
µ
A
CS=V
IH
, V
IN
=GND to V
CC
CS=V
IH
, V
OUT
=GND to V
CC
Tamb=25
°
C, F
CLK
=1.0 MHz,
V
CC
=5.5V (Note)
V
CC
=5.5V; SO=Open
V
CC
=2.5V; SO=Open
V
CC
=5.5V; SO=Open, F
CLK
=3.0 MHz
V
CC
=2.5V; SO=Open, F
CLK
=2.0 MHz
CS=V
CC
=5.5V; V
IN
=GND or V
CC
CS=V
CC
=2.5V; V
IN
=GND or V
CC
5
mA
3
mA
I
CC
Read
1
mA
500
µ
A
Standby Current
I
CCS
5
µ
A
µ
A
2
Note:
This parameter is periodically sampled and not 100% tested.
DS21157B-page 2
Preliminary
©
1996 Microchip Technology Inc.
25AA320
FIGURE 1-3: SERIAL INPUT TIMING
t
CSD
CS
t
CSS
SCK
t
SU
SI
msb in
t
HD
lsb in
t
R
t
CLD
t
F
t
CSH
SO
high impedance
FIGURE 1-4: SERIAL OUTPUT TIMING
CS
t
HI
SCK
t
V
SO
msb out
t
HO
t
DIS
lsb out
t
LO
t
CSH
SI
don’t care
FIGURE 1-5:
CS
HOLD TIMING
t
HS
SCK
t
HH
t
HS
t
HH
t
HZ
SO
n+2
n+1
n
high impedance
t
HV
n
t
SU
n
n-1
n-1
don’t care
SI
HOLD
n+2
n+1
n
©
1996 Microchip Technology Inc.
Preliminary
DS21157B-page 3
25AA320
TABLE 1-2:
AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = +1.8V to 5.5V
Commercial (C):
Tamb = 0°C to +70°C
Industrial (I)
Tamb = -40°C to +85°C
Symbol
fSCK
Parameter
Clock Frequency
Min
—
—
—
100
250
500
100
250
500
250
500
500
30
50
50
50
100
100
—
—
150
250
475
150
250
475
50
—
—
—
0
—
—
—
100
100
200
100
100
200
100
150
200
100
150
200
—
1M
Max
3
2
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
—
—
—
—
—
—
—
150
250
475
—
200
250
500
—
—
—
—
—
—
—
—
—
—
—
—
5
—
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
E/W Cycles
Test Conditions
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
(Note 1)
(Note 1)
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
(Note 2)
25°C, Vcc = 5.0V, Block Mode (Note 3)
tCSS
CS Setup Time
tCSH
CS Hold Time
tCSD
CS Disable Time
tSU
Data Setup Time
tHD
Data Hold Time
tR
tF
tHI
CLK Rise Time
CLK Fall Time
Clock High Time
tLO
Clock Low Time
tCLD
tV
Clock Delay Time
Output Valid from
Clock Low
Output Hold Time
Output Disable Time
tHO
tDIS
tHS
HOLD Setup Time
tHH
HOLD Hold Time
tHZ
HOLD Low to Output High-Z
tHV
HOLD High to Output Valid
tWC
—
Internal Write Cycle Time
Endurance
Note 1: This parameter is periodically sampled and not 100% tested.
2: tWC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write cycle is
complete.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our BBS or website.
DS21157B-page 4
Preliminary
©
1996 Microchip Technology Inc.
25AA320
2.0
PRINCIPLES OF OPERATION
2.2
Read Status Register (RDSR)
The 25AA320 is a 4096 byte EEPROM designed to
interface directly with the serial peripheral interface (SPI)
port of many of today’s popular microcontroller families,
including Microchip’s midrange PIC16CXX microcontrol-
lers. It may also interface with microcontrollers that do
not have a built-in SPI port by using discrete I/O lines
programmed properly with software.
The 25AA320 contains an 8-bit instruction register. The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. If the WPEN bit in the sta-
tus register is set, the WP pin must be held high to allow
writing to the non-volatile bits in the status register.
Table 2-1 contains a list of the possible instruction bytes
and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other peripheral
devices on the SPI bus, the user can assert the HOLD
input and place the 25AA320 in ‘HOLD’ mode. After
releasing the HOLD pin, operation will resume from the
point when the HOLD was asserted.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7
WPEN
6 5 4
X X X
3
BP1
2
BP0
1
WEL
0
WIP
The
Write-In-Process (WIP)
bit indicates whether the
25AA320 is busy with a write operation. When set to a
‘1’ a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.
The
Write Enable Latch (WEL)
bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array and status register, when set
to a ‘0’ the latch prohibits writes to the array and status
register. The state of this bit can always be updated via
the WREN or WRDI commands regardless of the state
of write protection on the status register. This bit is read
only.
The
Block Protection (BP0 and BP1)
bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
The
Write Protect Enable (WPEN)
bit is a non-volatile
bit that is available as an enable bit for the WP pin. The
Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the status register control the
programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
low and the WPEN bit is high. Hardware write
protection is disabled when either the WP pin is high or
the WPEN bit is low. When the chip is hardware write
protected, only writes to non-volatile bits in the status
register are disabled. See Table 2-2 for matrix of
functionality on the WPEN bit and Figure 2-1 for a
flowchart of Table 2-2.
See Figure 3-5 for RDSR timing sequence.
2.1
Write Enable (WREN) and Write
Disable (WRDI)
The 25AA320 contains a write enable latch. This latch
must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch. The following is
a list of conditions under which the write enable latch
will be reset:
•
•
•
•
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
TABLE 2-1:
INSTRUCTION SET
Description
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read status register
Write status register (write protect enable and block write protection bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Instruction Name Instruction Format
WREN
WRDI
RDSR
WRSR
READ
WRITE
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
©
1996 Microchip Technology Inc.
Preliminary
DS21157B-page 5
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