Dual 800mA Low Quiescent Current 2.25MHz High
Efficiency Synchronous Buck Regulator
ISL78228
The ISL78228 is a high efficiency, dual synchronous step-down
DC/DC regulator that can deliver up to 800mA continuous
output current per channel. The supply voltage range of 2.75V
to 5.5V allows for the use of a 3.3V or 5V input. The current
mode control architecture enables very low duty cycle
operation at high frequency with fast transient response and
excellent loop stability. The ISL78228 operates above the AM
radio band as well as the 2.25MHz switching frequency,
allowing for the use of small, low cost inductors and
capacitors. Each channel is optimized for generating an output
voltage as low as 0.6V.
The ISL78228 has a user configurable mode of
operation-forced PWM mode and PFM/PWM mode. The forced
PWM mode operation reduces noise and RF interference while
the PFM mode operation provides high efficiency by reducing
switching losses at light loads. In PFM mode of operation, both
channels draw a total quiescent current of only 30µA, hence
enabling high light load efficiency in order to maximize battery
life.
The ISL78228 offers a 1ms Power-Good (PG) to monitor both
outputs at power-up. When shutdown, ISL78228 discharges
the outputs capacitor. Other features include internal digital
soft-start, enable for power sequence, overcurrent protection,
and thermal shutdown. The ISL78228 is offered in a
3mmx3mm 10 Ld DFN package with 1mm maximum height.
The complete converter occupies less than 1.8cm
2
area.
The ISL78228 is both AEC - Q100 rated and fully TS16949
compliant. The ISL78228 is rated for the automotive
temperature range (-40°C to +105°C).
Features
• Internal Current Mode Compensation
• 100% Maximum Duty Cycle for Lowest Dropout
• Selectable Forced PWM Mode and PFM Mode
• External Synchronization up to 4MHz
• Start-up with Pre-biased Output
• Soft-Stop Output Discharge During Disabled
• Internal Digital Soft-Start - 2ms
• Power-Good (PG) Output with 1ms Delay
• TS16949 Compliant
• AEC - Q100 Tested
• Pb-free (RoHS Compliant)
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Rear Camera Systems
• Navigation Systems
• Infotainment Systems
100
90
EFFICIENCY (%)
80
70
60
50
40
1.8V
OUT
-PWM
VIN = 5V
0.0
0.1
0.2
0.3
0.4
0.5
OUTPUT LOAD (A)
0.6
0.7
0.8
1.8V
OUT
-PFM
2.5V
OUT
-PWM
2.5V
OUT
-PFM
FIGURE 1. EFFICIENCY CHARACTERISTICS CURVE
May 2, 2011
FN7849.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78228
Typical Application
L1
2.2µH
LX1
C2
10µF
PGND
INPUT 2.75V TO 5.5V
VIN
C1
10µF
EN1
ISL78228
EN2
LX2
PG
PGND
C4
10µF
R5
200k
L2
2.2µH
R2
316k
OUTPUT1
2.5V/800mA
C3
10pF
FB1
R3
100k
OUTPUT2
1.8V/800mA
C5
10pF
SYNC
FB2
R6
100k
PGND
2
FN7849.0
May 2, 2011
ISL78228
Pin Configuration
ISL78228
(10 LD 3X3 DFN)
TOP VIEW
FB1
EN1
VIN
LX1
NC
1
2
3
4
5
PAD
10 FB2
9
8
7
6
EN2
PG
LX2
SYNC
Pin Descriptions
DFN
1
SYMBOL
FB1
DESCRIPTION
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to any
voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1
regulator output voltage.
Regulator Channel 1 enable pin. Enable the output, V
OUT1
, when driven to high. Shutdown the V
OUT1
and discharge output
capacitor when driven to low. Do not leave this pin floating.
Input supply voltage. Connect 10µF ceramic capacitor to power ground.
Switching node connection for Channel 1. Connect to one terminal of inductor for V
OUT1
.
Recommended to connect this pin to the exposed pad.
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode.
Connect to an external function generator for Synchronization, and negative edge trigger. Do not leave this pin floating.
Switching node connection for Channel 2. Connect to one terminal of inductor for V
OUT2
.
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the V
OUT1
and V
OUT2
voltages.
There is an internal 1MΩ pull-up resistor.
Regulator Channel 2 enable pin. Enable the output, V
OUT2
, when driven to high. Shutdown the V
OUT2
and discharge output
capacitor when driven to low. Do not leave this pin floating.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to any
voltage between the power-rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2 regulator output voltage.
The exposed pad must be connected to PGND for proper electrical performance. Add as much vias as possible for optimal thermal
performance.
2
3
4
5
6
7
8
9
10
EN1
VIN
LX1
NC
SYNC
LX2
PG
EN2
FB2
-
PAD
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL78228ARZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL78228.
For more information on MSL please see techbrief
TB363.
8228
PART
MARKING
TEMP. RANGE
(°C)
-40 to +105
PACKAGE
(Pb-Free)
10 Ld 3x3 DFN
L10.3x3C
PKG.
DWG. #
3
FN7849.0
May 2, 2011
ISL78228
Absolute Maximum Ratings
(Reference to GND)
Supply Voltage (V
IN
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V (20ms)
EN1, EN2, PG, SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to V
IN
+ 0.3V
LX1, LX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V (100ns)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to 7V (20ms)
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 300V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD78C; Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
10 Ld 3x3 DFN Package (Notes 4, 5) . . . . . .
49
4
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
V
IN
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75V to 5.5V
Load Current Range Per Channel . . . . . . . . . . . . . . . . . . . . . 0mA to 800mA
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Unless otherwise noted, all parameter limits are established over the recommended operating
conditions: T
A
= -40°C to +105°C, V
IN
= 2.75V to 5.5V, EN1 = EN2 = V
IN
, SYNC = 0V, L = 2.2µH, C
1
= 10µF, C
2
= C
4
= 10µF,
I
OUT1
= I
OUT2
= 0A to 800mA. (Typical values are at T
A
= +25°C, V
IN
= 3.6V). Boldface limits apply over the operating temperature range,
-40°C to +105°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Electrical Specifications
INPUT SUPPLY
V
IN
Undervoltage Lockout Threshold
V
UVLO
Rising
Falling
Quiescent Supply Current
I
VIN
SYNC = V
IN
, EN1 = EN2 = V
IN
, no load at the
output and no switches switching.
VFB1 = VFB2 = 0.7V
SYNC = GND, EN1 = EN2 = VIN,
F
S
= 2.25MHz, no load at the output
Shut Down Supply Current
I
SD
V
IN
= 5.5V, EN1 = EN2 = GND
2.1
2.5
2.4
30
50
2.75
V
V
µA
0.1
6.5
1
12
mA
µA
OUTPUT REGULATION
FB1, FB2 Regulation Voltage
FB1, FB2 Bias Current
Line Regulation
Soft-Start Ramp Time Cycle
V
FB_
I
FB_
VFB = 0.55V
V
IN
= V
O
+ 0.5V to 5.5V (minimal 2.75V,
I
OUT
= 0A)
0.590
0.6
0.1
0.2
2
0.610
V
µA
%/V
ms
OVERCURRENT PROTECTION
Peak Overcurrent Limit
I
pk1
I
pk2
Peak SKIP Limit
I
skip1
I
skip2
V
IN
= 3.6V
0.95
0.95
180
180
1.2
1.2
250
250
1.6
1.6
360
360
A
A
mA
mA
LX1, LX2
P-Channel MOSFET ON-Resistance
V
IN
= 5.5V, I
O
= 200mA
V
IN
= 2.75V, I
O
= 200mA
N-Channel MOSFET ON-Resistance
V
IN
= 5.5V, I
O
= 200mA
V
IN
= 2.75V, I
O
= 200mA
180
320
180
320
350
450
350
450
mΩ
mΩ
mΩ
mΩ
4
FN7849.0
May 2, 2011
ISL78228
Unless otherwise noted, all parameter limits are established over the recommended operating
conditions: T
A
= -40°C to +105°C, V
IN
= 2.75V to 5.5V, EN1 = EN2 = V
IN
, SYNC = 0V, L = 2.2µH, C
1
= 10µF, C
2
= C
4
= 10µF,
I
OUT1
= I
OUT2
= 0A to 800mA. (Typical values are at T
A
= +25°C, V
IN
= 3.6V). Boldface limits apply over the operating temperature range,
-40°C to +105°C. (Continued)
PARAMETER
LX_ Maximum Duty Cycle
PWM Switching Frequency
Synchronization Range
LX Minimum On-Time
Soft Discharge Resistance
R
DIS_
SYNC = 0 (forced PWM mode)
EN = LOW
80
100
F
S
1.8
2.7
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
100
2.25
2.7
4
100
130
MAX
(Note 6)
UNITS
%
MHz
MHz
ns
Ω
Electrical Specifications
PG
Output Low Voltage
PG Pull-up Resistor
Internal P
GOOD
Low Rising Threshold
Internal P
GOOD
Low Falling Threshold
Delay Time (Rising Edge)
Internal P
GOOD
Delay Time (Falling Edge)
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
88
82
Sinking 1mA, VFB = 0.5V
1
92
89
1
1
2
96
91
0.3
V
MΩ
%
%
ms
µs
EN1, EN2, SYNC
Logic Input Low
Logic Input High
SYNC Logic Input Leakage Current
Enable Logic Input Leakage Current
Thermal Shutdown
Thermal Shutdown Hysteresis
I
SYNC
I
EN_
Pulled up to 5.5V
1.4
0.1
0.1
150
25
1
1
0.4
V
V
µA
µA
°C
°C
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5
FN7849.0
May 2, 2011
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