74CBTLVD3384
10-bit level-shifting bus switch with 5-bit output enables
Rev. 2 — 16 December 2011
Product data sheet
1. General description
The 74CBTLVD3384 is a dual 5-pole, single-throw bus switch. The device features two
output enable inputs (nOE) that each control five switch channels. The switches are
disabled when the associated nOE input is HIGH. Schmitt-trigger action at control inputs
makes the circuit tolerant of slower input rise and fall times. This device is fully specified
for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits
Supply voltage range from 3.0 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-B/JESD36 (3.0 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5
switch connection between two ports
3
dB bandwidth at 600 MHz
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74CBTLVD3384
10-bit level-shifting bus switch with 5-bit output enables
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74CBTLVD3384DK
Name
Description
plastic shrink small outline package; 24 leads;
body width 3.9 mm; lead pitch 0.635 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT556-1
SOT355-1
SOT815-1
Type number
40 C
to +125
C
SSOP24
[1]
74CBTLVD3384PW
40 C
to +125
C
TSSOP24
74CBTLVD3384BQ
40 C
to +125
C
DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5
5.5
0.85 mm
[1]
Also known as QSOP24 package
4. Functional diagram
1A1
3
1OE
1
1A2
4
1A3
7
1A4
8
1A5
11
2
1B1
5
1B2
6
1B3
9
1B4
10
1B5
2A1
14
2OE
13
2A2
17
2A3
18
2A4
21
2A5
22
15
2B1
16
2B2
19
2B3
20
2B4
23
2B5
001aam095
Fig 1.
Logic symbol
74CBTLVD3384
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 16 December 2011
2 of 20
NXP Semiconductors
74CBTLVD3384
10-bit level-shifting bus switch with 5-bit output enables
1A1
3
2
1B1
1A5
11
10
1B5
1OE
1
2A1
14
15
2B1
2A5
22
23
2B5
2OE
13
001aak877
Fig 2.
Logic diagram
5. Pinning information
5.1 Pinning
74CBTLVD3384
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1
2
3
4
5
6
7
8
9
24 V
CC
23 2B5
22 2A5
21 2A4
20 2B4
19 2B3
18 2A3
17 2A2
16 2B2
15 2B1
14 2A1
13 2OE
001aam099
74CBTLVD3384
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1
2
3
4
5
6
7
8
9
24 V
CC
23 2B5
22 2A5
21 2A4
20 2B4
19 2B3
18 2A3
17 2A2
16 2B2
15 2B1
14 2A1
13 2OE
001aam100
1B5 10
1A5 11
GND 12
1B5 10
1A5 11
GND 12
Fig 3.
Pin configuration for TSSOP24 (SOT355-1)
Fig 4.
Pin configuration for SSOP24 (SOT556-1)
74CBTLVD3384
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 16 December 2011
3 of 20
NXP Semiconductors
74CBTLVD3384
10-bit level-shifting bus switch with 5-bit output enables
74CBTLVD3384
1OE
terminal 1
index area
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
2
3
4
5
6
7
8
9
GND
(1)
GND 12
2OE 13
24 V
CC
23 2B5
22 2A5
21 2A4
20 2B4
19 2B3
18 2A3
17 2A2
16 2B2
15 2B1
14 2A1
1B5 10
1A5 11
1
001aam101
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 5.
Pin configuration for DHVQFN24 (SOT815-1)
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
1A1 to 1A5
2A1 to 2A5
1B1 to 1B5
2B1 to 2B5
GND
V
CC
Pin description
Pin
1, 13
3, 4, 7, 8, 11
14, 17, 18, 21, 22
2, 5, 6, 9, 10
15, 16, 19, 20, 23
12
24
Description
output enable input (active LOW)
data input/output (A port)
data input/output (A port)
data input/output (B port)
data input/output (B port)
ground (0 V)
positive supply voltage
6. Functional description
Table 3.
Input
1OE
L
L
H
H
[1]
Function selection
[1]
Input/output
2OE
L
H
L
H
1An, 1Bn
1An = 1Bn
1An = 1Bn
Z
Z
2An, 2Bn
2An = 2Bn
Z
2An = 2Bn
Z
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
74CBTLVD3384
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 16 December 2011
4 of 20
NXP Semiconductors
74CBTLVD3384
10-bit level-shifting bus switch with 5-bit output enables
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
enable and disable mode
V
I/O
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SSOP24 and TSSOP24 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN24 package: P
tot
derates linearly at 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
[1]
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.0 V to 3.6 V
[1]
Conditions
Min
3.0
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
enable and disable mode
0
40
0
Applies to control signal levels.
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
I
I
V
pass
HIGH-level
input voltage
LOW-level
input voltage
input leakage
current
pass voltage
Conditions
V
CC
= 3.0 V to 3.6 V
V
CC
= 3.0 V to 3.6 V
pin nOE; V
I
= GND to V
CC
;
V
CC
= 3.6 V
V
I
= V
CC
; see
Figure 9
to
Figure 12
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +125
C
Unit
Min
2.0
-
-
-
Typ
[1]
-
-
-
-
Max
-
0.9
1
-
Min
2.0
-
-
-
Max
-
0.9
20
-
V
V
A
V
74CBTLVD3384
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 16 December 2011
5 of 20
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